Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index be0b262783ff11244ae46bc9e92b800292767a95..868771a167689c94b8dc5849f47467f399f89a3a 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -595,8 +595,8 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
     : I<4, OL, asmstr, itin> {
   bits<5> VD;
   bits<5> VA;
-  bits<5> VB;
   bits<5> VC;
+  bits<5> VB;
 
   let Pattern = pattern;
   

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 3d0a30d0a859cbb4fba56726d50ceb53cf9d486f..181f156564095d5bd632fe47abdbe3b15313a5d8 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -948,22 +948,21 @@ def RLDICR : MDForm_1<30, 1,
 
 let PPC970_Unit = 5 in {  // VALU Operations.
 // VA-Form instructions.  3-input AltiVec ops.
-def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
                        "vmaddfp $vD, $vA, $vC, $vB", VecFP,
                        [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
                                              VRRC:$vB))]>,
                        Requires<[FPContractions]>;
-def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
                        "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
-                       [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, 
-                                                         VRRC:$vC),
-                                                  VRRC:$vB)))]>,
+                       [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
+                                                   VRRC:$vB)))]>,
                        Requires<[FPContractions]>;
 
-def VPERM   : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                       "vperm $vD, $vA, $vB, $vC", VecPerm,
+def VPERM   : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
+                       "vperm $vD, $vA, $vC, $vB", VecPerm,
                        [(set VRRC:$vD,
-                             (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
+                             (PPCvperm (v4f32 VRRC:$vA), VRRC:$vC, VRRC:$vB))]>;
 
 
 // VX-Form instructions.  AltiVec arithmetic ops.