implementation of some methods for inlineasm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25951 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5a191d999814760fb3b2490697177b91a5700c8f..068f6a8f5d2c8f77c73693310530b7653c8ef33c 100644 (file)
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -131,6 +131,10 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
   return NULL;
 }
 
+//===----------------------------------------------------------------------===//
+//  Optimization Methods
+//===----------------------------------------------------------------------===//
+
 /// DemandedBitsAreZero - Return true if 'Op & Mask' demands no bits from a bit
 /// set operation such as a sign extend or or/xor with constant whose only
 /// use is Op.  If it returns true, the old node that sets bits which are
@@ -139,7 +143,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
 /// desired.
 bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask, 
                                          SDOperand &Old, SDOperand &New,
-                                         SelectionDAG &DAG) {
+                                         SelectionDAG &DAG) const {
   // If the operation has more than one use, we're not interested in it.
   // Tracking down and checking all uses would be problematic and slow.
   if (!Op.Val->hasOneUse())
@@ -302,6 +306,42 @@ bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
   return false;
 }
 
+//===----------------------------------------------------------------------===//
+//  Inline Assembler Implementation Methods
+//===----------------------------------------------------------------------===//
+
+TargetLowering::ConstraintType
+TargetLowering::getConstraintType(char ConstraintLetter) const {
+  // FIXME: lots more standard ones to handle.
+  switch (ConstraintLetter) {
+  default: return C_Unknown;
+  case 'r': return C_RegisterClass;
+  case 'i':    // Simple Integer or Relocatable Constant
+  case 'n':    // Simple Integer
+  case 's':    // Relocatable Constant
+  case 'I':    // Target registers.
+  case 'J':
+  case 'K':
+  case 'L':
+  case 'M':
+  case 'N':
+  case 'O':
+  case 'P':  return C_Other;
+  }
+}
+
+bool TargetLowering::isOperandValidForConstraint(SDOperand Op, 
+                                                 char ConstraintLetter) {
+  switch (ConstraintLetter) {
+  default: return false;
+  case 'i':    // Simple Integer or Relocatable Constant
+  case 'n':    // Simple Integer
+  case 's':    // Relocatable Constant
+    return true;   // FIXME: not right.
+  }
+}
+
+
 std::vector<unsigned> TargetLowering::
 getRegForInlineAsmConstraint(const std::string &Constraint) const {
   // Not a physreg, must not be a register reference or something.