#clock-cells = <0>;
rockchip,flags = <(CLK_GET_RATE_NOCACHE |
CLK_SET_RATE_NO_REPARENT)>;
- rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
+ rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
};
/* reg[7:2]: reserved */
#include <linux/rockchip/grf.h>
#include <linux/rockchip/iomap.h>
#include <linux/clk-private.h>
+#include <linux/rockchip/cpu.h>
#include "../../../drivers/clk/rockchip/clk-pd.h"
#include "cpu_axi.h"
real_rate *= MHZ;
if (!real_rate)
return -EAGAIN;
-
- clk->parent->rate = clk->rate = real_rate;
+ if (cpu_is_rk312x()) {
+ clk->parent->rate = 2 * real_rate;
+ clk->rate = real_rate;
+ } else {
+ clk->rate = real_rate;
+ clk->parent->rate = real_rate;
+ }
return 0;
}
}
- DVFS_DBG("%s:clk(%s) last_set_rate=%u; [min_rate, max_rate]=[%u, %u]\n",
- __func__, __clk_get_name(clk_dvfs_node->clk), clk_dvfs_node->last_set_rate,
- clk_dvfs_node->min_rate, clk_dvfs_node->max_rate);
+ DVFS_DBG("%s:clk(%s) last_set_rate=%lu; [min_rate, max_rate]=[%u, %u]\n",
+ __func__, __clk_get_name(clk_dvfs_node->clk),
+ clk_dvfs_node->last_set_rate,
+ clk_dvfs_node->min_rate, clk_dvfs_node->max_rate);
return 0;
}
mutex_unlock(&clk_dvfs_node->vd->mutex);
}
- DVFS_DBG("%s: clk(%s) last_set_rate=%u; [min_rate, max_rate]=[%u, %u]\n",
- __func__, __clk_get_name(clk_dvfs_node->clk), clk_dvfs_node->last_set_rate, clk_dvfs_node->min_rate, clk_dvfs_node->max_rate);
+ DVFS_DBG("%s: clk(%s) last_set_rate=%lu; [min_rate, max_rate]=[%u, %u]\n",
+ __func__, __clk_get_name(clk_dvfs_node->clk),
+ clk_dvfs_node->last_set_rate,
+ clk_dvfs_node->min_rate, clk_dvfs_node->max_rate);
+
return 0;
}
EXPORT_SYMBOL(dvfs_clk_disable_limit);
if (!clk)
return -EINVAL;
- if (!clk_dvfs_node->enable_count){
- DVFS_WARNING("%s:dvfs(%s) is disable\n",
- __func__, clk_dvfs_node->name);
+ if (!clk_dvfs_node->enable_count)
return 0;
- }
if (clk_dvfs_node->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {
/* It means the last time set voltage error */
.determine_rate = clk_ddr_determine_rate,
};
+static unsigned long clk_ddr_div2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ /* Same as clk_core, we should NOT set clk_ddr's parent
+ * (dpll) rate directly as a side effect.
+ */
+ struct clk *parent = __clk_get_parent(hw->clk);
+
+ return clk_divider_recalc_rate(hw, __clk_get_rate(parent))/2;
+}
+
+const struct clk_ops clkops_rate_ddr_div2 = {
+ .recalc_rate = clk_ddr_div2_recalc_rate,
+ .round_rate = clk_ddr_round_rate,
+ .set_rate = clk_ddr_set_rate,
+ .determine_rate = clk_ddr_determine_rate,
+};
+
static unsigned long clk_3288_i2s_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
{.index = CLKOPS_RATE_RK3288_USB480M, .clk_ops = &clkops_rate_3288_usb480m},
{.index = CLKOPS_RATE_RK3288_DCLK_LCDC0,.clk_ops = &clkops_rate_3288_dclk_lcdc0},
{.index = CLKOPS_RATE_RK3288_DCLK_LCDC1,.clk_ops = &clkops_rate_3288_dclk_lcdc1},
+ {.index = CLKOPS_RATE_DDR_DIV2, .clk_ops = &clkops_rate_ddr_div2},
{.index = CLKOPS_RATE_I2S, .clk_ops = NULL},
{.index = CLKOPS_RATE_CIFOUT, .clk_ops = NULL},
{.index = CLKOPS_RATE_UART, .clk_ops = NULL},
#define CLKOPS_RATE_RK3288_USB480M 15
#define CLKOPS_RATE_RK3288_DCLK_LCDC0 16
#define CLKOPS_RATE_RK3288_DCLK_LCDC1 17
+#define CLKOPS_RATE_DDR_DIV2 18
#define CLKOPS_TABLE_END (~0)
/* pd id */