for the device and attempt to bind to it. For example:
# echo "8086 10f5" > /sys/bus/usb/drivers/foo/new_id
+ Reading from this file will list all dynamically added
+ device IDs in the same format, with one entry per
+ line. For example:
+ # cat /sys/bus/usb/drivers/foo/new_id
+ 8086 10f5
+ dead beef 06
+ f00d cafe
+
+ The list will be truncated at PAGE_SIZE bytes due to
+ sysfs restrictions.
+
What: /sys/bus/usb-serial/drivers/.../new_id
Date: October 2011
Contact: linux-usb@vger.kernel.org
match the driver to the device. For example:
# echo "046d c315" > /sys/bus/usb/drivers/foo/remove_id
+ Reading from this file will list the dynamically added
+ device IDs, exactly like reading from the entry
+ "/sys/bus/usb/drivers/.../new_id"
+
What: /sys/bus/usb/device/.../avoid_reset_quirk
Date: December 2009
Contact: Oliver Neukum <oliver@neukum.org>
Description:
Some information about whether a given USB device is
physically fixed to the platform can be inferred from a
- combination of hub decriptor bits and platform-specific data
+ combination of hub descriptor bits and platform-specific data
such as ACPI. This file will read either "removable" or
"fixed" if the information is available, and "unknown"
- otherwise.
+ otherwise.
F: drivers/amba/
F: include/linux/amba/bus.h
-ARM/ADI ROADRUNNER MACHINE SUPPORT
-M: Lennert Buytenhek <kernel@wantstofly.org>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-F: arch/arm/mach-ixp23xx/
-F: arch/arm/mach-ixp23xx/include/mach/
-
ARM/ADS SPHERE MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-prima2/
-F: drivers/dma/sirf-dma*
+F: drivers/dma/sirf-dma.c
+F: drivers/i2c/busses/i2c-sirf.c
+F: drivers/pinctrl/pinctrl-sirf.c
+F: drivers/spi/spi-sirf.c
ARM/EBSA110 MACHINE SUPPORT
M: Russell King <linux@arm.linux.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
-ARM/INTEL IXP2000 ARM ARCHITECTURE
-M: Lennert Buytenhek <kernel@wantstofly.org>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-
ARM/INTEL IXDP2850 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
-ARM/INTEL IXP23XX ARM ARCHITECTURE
-M: Lennert Buytenhek <kernel@wantstofly.org>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-
ARM/INTEL IXP4XX ARM ARCHITECTURE
M: Imre Kaloz <kaloz@openwrt.org>
M: Krzysztof Halasa <khc@pm.waw.pl>
M: Philipp Zabel <philipp.zabel@gmail.com>
S: Maintained
-ARM/Marvell Loki/Kirkwood/MV78xx0/Orion SOC support
-M: Lennert Buytenhek <kernel@wantstofly.org>
-M: Nicolas Pitre <nico@fluxnic.net>
+ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
+M: Jason Cooper <jason@lakedaemon.net>
+M: Andrew Lunn <andrew@lunn.ch>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Odd Fixes
+S: Maintained
+F: arch/arm/mach-dove/
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mv78xx0/
F: arch/arm/mach-orion5x/
S: Supported
F: drivers/tty/serial/atmel_serial.c
+ATMEL DMA DRIVER
+M: Nicolas Ferre <nicolas.ferre@atmel.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Supported
+F: drivers/dma/at_hdmac.c
+F: drivers/dma/at_hdmac_regs.h
+F: arch/arm/mach-at91/include/mach/at_hdmac.h
+
+ATMEL ISI DRIVER
+M: Josh Wu <josh.wu@atmel.com>
+L: linux-media@vger.kernel.org
+S: Supported
+F: drivers/media/video/atmel-isi.c
+F: include/media/atmel-isi.h
+
ATMEL LCDFB DRIVER
M: Nicolas Ferre <nicolas.ferre@atmel.com>
L: linux-fbdev@vger.kernel.org
S: Supported
F: drivers/spi/spi-atmel.*
+ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS
+M: Nicolas Ferre <nicolas.ferre@atmel.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Supported
+F: drivers/misc/atmel_tclib.c
+F: drivers/clocksource/tcb_clksrc.c
+
+ATMEL TSADCC DRIVER
+M: Josh Wu <josh.wu@atmel.com>
+L: linux-input@vger.kernel.org
+S: Supported
+F: drivers/input/touchscreen/atmel_tsadcc.c
+
ATMEL USBA UDC DRIVER
M: Nicolas Ferre <nicolas.ferre@atmel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W: http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver
S: Supported
F: drivers/usb/gadget/atmel_usba_udc.*
BATMAN ADVANCED
M: Marek Lindner <lindner_marek@yahoo.de>
M: Simon Wunderlich <siwu@hrz.tu-chemnitz.de>
+M: Antonio Quartulli <ordex@autistici.org>
L: b.a.t.m.a.n@lists.open-mesh.org
W: http://www.open-mesh.org/
S: Maintained
M: Johan Hedberg <johan.hedberg@gmail.com>
L: linux-bluetooth@vger.kernel.org
W: http://www.bluez.org/
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/padovan/bluetooth.git
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jh/bluetooth.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git
S: Maintained
F: drivers/bluetooth/
M: Johan Hedberg <johan.hedberg@gmail.com>
L: linux-bluetooth@vger.kernel.org
W: http://www.bluez.org/
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/padovan/bluetooth.git
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jh/bluetooth.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git
S: Maintained
F: net/bluetooth/
F: include/net/bluetooth/
BROCADE BFA FC SCSI DRIVER
M: Jing Huang <huangj@brocade.com>
+M: Krishna C Gudipati <kgudipat@brocade.com>
L: linux-scsi@vger.kernel.org
S: Supported
F: drivers/scsi/bfa/
F: include/linux/capability.h
F: security/capability.c
F: security/commoncap.c
+F: kernel/capability.c
CELL BROADBAND ENGINE ARCHITECTURE
M: Arnd Bergmann <arnd@arndb.de>
S: Maintained
F: Documentation/zh_CN/
+CHIPIDEA USB HIGH SPEED DUAL ROLE CONTROLLER
+M: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+L: linux-usb@vger.kernel.org
+S: Maintained
+F: drivers/usb/chipidea/
+
CISCO VIC ETHERNET NIC DRIVER
M: Christian Benvenuti <benve@cisco.com>
M: Roopa Prabhu <roprabhu@cisco.com>
F: drivers/net/ethernet/ti/cpmac.c
CPU FREQUENCY DRIVERS
-M: Dave Jones <davej@redhat.com>
+M: Rafael J. Wysocki <rjw@sisk.pl>
L: cpufreq@vger.kernel.org
-W: http://www.codemonkey.org.uk/projects/cpufreq/
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git
+L: linux-pm@vger.kernel.org
S: Maintained
F: drivers/cpufreq/
F: include/linux/cpufreq.h
F: drivers/acpi/dock.c
DOCUMENTATION
-M: Randy Dunlap <rdunlap@xenotime.net>
+M: Rob Landley <rob@landley.net>
L: linux-doc@vger.kernel.org
-T: quilt http://xenotime.net/kernel-doc-patches/current/
+T: TBD
S: Maintained
F: Documentation/
F: arch/frv/
FUJITSU LAPTOP EXTRAS
- M: Jonathan Woithe <jwoithe@physics.adelaide.edu.au>
+ M: Jonathan Woithe <jwoithe@just42.net>
L: platform-driver-x86@vger.kernel.org
S: Maintained
F: drivers/platform/x86/fujitsu-laptop.c
M: Jonathan Cameron <jic23@cam.ac.uk>
L: linux-iio@vger.kernel.org
S: Maintained
+F: drivers/iio/
F: drivers/staging/iio/
IKANOS/ADI EAGLE ADSL USB DRIVER
S: Maintained
F: drivers/char/hw_random/ixp4xx-rng.c
-INTEL IXP2000 ETHERNET DRIVER
-M: Lennert Buytenhek <kernel@wantstofly.org>
-L: netdev@vger.kernel.org
-S: Maintained
-F: drivers/net/ethernet/xscale/ixp2000/
-
INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/igbvf/ixgb/ixgbe/ixgbevf)
M: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
M: Jesse Brandeburg <jesse.brandeburg@intel.com>
F: drivers/net/wireless/iwlegacy/
INTEL WIRELESS WIFI LINK (iwlwifi)
+M: Johannes Berg <johannes.berg@intel.com>
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
W: http://wireless.kernel.org/en/users/Drivers/iwmc3200wifi
F: drivers/net/wireless/iwmc3200wifi/
+INTEL MANAGEMENT ENGINE (mei)
+M: Tomas Winkler <tomas.winkler@intel.com>
+L: linux-kernel@vger.kernel.org
+S: Supported
+F: include/linux/mei.h
+F: drivers/misc/mei/*
+F: Documentation/mei/*
+
IOC3 ETHERNET DRIVER
M: Ralf Baechle <ralf@linux-mips.org>
L: linux-mips@linux-mips.org
F: drivers/net/ethernet/icplus/ipg.*
IPATH DRIVER
-M: Mike Marciniszyn <infinipath@qlogic.com>
+M: Mike Marciniszyn <infinipath@intel.com>
L: linux-rdma@vger.kernel.org
S: Maintained
F: drivers/infiniband/hw/ipath/
F: drivers/scsi/53c700*
LED SUBSYSTEM
+M: Bryan Wu <bryan.wu@canonical.com>
M: Richard Purdie <rpurdie@rpsys.net>
S: Maintained
F: drivers/leds/
F: drivers/net/ethernet/myricom/myri10ge/
NATSEMI ETHERNET DRIVER (DP8381x)
-M: Tim Hockin <thockin@hockin.org>
-S: Maintained
+S: Orphan
F: drivers/net/ethernet/natsemi/natsemi.c
NATIVE INSTRUMENTS USB SOUND INTERFACE DRIVER
F: arch/arm/mach-omap2/clockdomain44xx.c
OMAP AUDIO SUPPORT
+M: Peter Ujfalusi <peter.ujfalusi@ti.com>
M: Jarkko Nikula <jarkko.nikula@bitmer.com>
L: alsa-devel@alsa-project.org (subscribers-only)
L: linux-omap@vger.kernel.org
F: include/linux/i2c-algo-pca.h
F: include/linux/i2c-pca-platform.h
+PCDP - PRIMARY CONSOLE AND DEBUG PORT
+M: Khalid Aziz <khalid.aziz@hp.com>
+S: Maintained
+F: drivers/firmware/pcdp.*
+
PCI ERROR RECOVERY
M: Linas Vepstas <linasvepstas@gmail.com>
L: linux-pci@vger.kernel.org
PCI SUBSYSTEM
M: Bjorn Helgaas <bhelgaas@google.com>
L: linux-pci@vger.kernel.org
-Q: http://patchwork.kernel.org/project/linux-pci/list/
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci.git
+Q: http://patchwork.ozlabs.org/project/linux-pci/list/
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/linux.git
S: Supported
F: Documentation/PCI/
F: drivers/pci/
F: include/linux/pci*
-PCI HOTPLUG
-M: Bjorn Helgaas <bhelgaas@google.com>
-L: linux-pci@vger.kernel.org
-S: Supported
-F: drivers/pci/hotplug
-
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
L: linux-pcmcia@lists.infradead.org
F: include/linux/personality.h
PHONET PROTOCOL
-M: Remi Denis-Courmont <remi.denis-courmont@nokia.com>
+M: Remi Denis-Courmont <courmisch@gmail.com>
S: Supported
F: Documentation/networking/phonet.txt
F: include/linux/phonet.h
S: Maintained
F: drivers/pinctrl/
+PIN CONTROLLER - ST SPEAR
+M: Viresh Kumar <viresh.kumar@st.com>
+L: spear-devel@list.st.com
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+W: http://www.st.com/spear
+S: Maintained
+F: driver/pinctrl/spear/
+
PKTCDVD DRIVER
M: Peter Osterlund <petero2@telia.com>
S: Maintained
S: Maintained
QIB DRIVER
-M: Mike Marciniszyn <infinipath@qlogic.com>
+M: Mike Marciniszyn <infinipath@intel.com>
L: linux-rdma@vger.kernel.org
S: Supported
F: drivers/infiniband/hw/qib/
READ-COPY UPDATE (RCU)
M: Dipankar Sarma <dipankar@in.ibm.com>
M: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
-W: http://www.rdrop.com/users/paulmck/rclock/
+W: http://www.rdrop.com/users/paulmck/RCU/
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
F: Documentation/RCU/
+X: Documentation/RCU/torture.txt
F: include/linux/rcu*
-F: include/linux/srcu*
F: kernel/rcu*
-F: kernel/srcu*
X: kernel/rcutorture.c
REAL TIME CLOCK (RTC) SUBSYSTEM
F: drivers/scsi/st*
SCTP PROTOCOL
-M: Vlad Yasevich <vladislav.yasevich@hp.com>
+M: Vlad Yasevich <vyasevich@gmail.com>
M: Sridhar Samudrala <sri@us.ibm.com>
L: linux-sctp@vger.kernel.org
W: http://lksctp.sourceforge.net
-S: Supported
+S: Maintained
F: Documentation/networking/sctp.txt
F: include/linux/sctp.h
F: include/net/sctp/
M: James Morris <james.l.morris@oracle.com>
L: linux-security-module@vger.kernel.org (suggested Cc:)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git
-W: http://security.wiki.kernel.org/
+W: http://kernsec.org/
S: Supported
F: security/
F: include/linux/sl?b*.h
F: mm/sl?b.c
+SLEEPABLE READ-COPY UPDATE (SRCU)
+M: Lai Jiangshan <laijs@cn.fujitsu.com>
+M: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
+W: http://www.rdrop.com/users/paulmck/RCU/
+S: Supported
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
+F: include/linux/srcu*
+F: kernel/srcu*
+
SMC91x ETHERNET DRIVER
M: Nicolas Pitre <nico@fluxnic.net>
S: Odd Fixes
F: arch/arm/plat-spear/clock.c
F: arch/arm/plat-spear/include/plat/clock.h
-SPEAR PAD MULTIPLEXING SUPPORT
-M: Viresh Kumar <viresh.kumar@st.com>
-L: spear-devel@list.st.com
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W: http://www.st.com/spear
-S: Maintained
-F: arch/arm/plat-spear/include/plat/padmux.h
-F: arch/arm/plat-spear/padmux.c
-F: arch/arm/mach-spear*/spear*xx.c
-F: arch/arm/mach-spear*/include/mach/generic.h
-F: arch/arm/mach-spear3xx/spear3*0.c
-F: arch/arm/mach-spear3xx/spear3*0_evb.c
-F: arch/arm/mach-spear6xx/spear600.c
-F: arch/arm/mach-spear6xx/spear600_evb.c
-
SPI SUBSYSTEM
M: Grant Likely <grant.likely@secretlab.ca>
L: spi-devel-general@lists.sourceforge.net
F: drivers/staging/olpc_dcon/
STAGING - OZMO DEVICES USB OVER WIFI DRIVER
+M: Rupesh Gujare <rgujare@ozmodevices.com>
M: Chris Kelly <ckelly@ozmodevices.com>
S: Maintained
F: drivers/staging/ozwpan/
S: Maintained
F: sound/soc/codecs/twl4030*
+TI WILINK WIRELESS DRIVERS
+M: Luciano Coelho <coelho@ti.com>
+L: linux-wireless@vger.kernel.org
+W: http://wireless.kernel.org/en/users/Drivers/wl12xx
+W: http://wireless.kernel.org/en/users/Drivers/wl1251
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/luca/wl12xx.git
+S: Maintained
+F: drivers/net/wireless/ti/
+F: include/linux/wl12xx.h
+
TIPC NETWORK LAYER
M: Jon Maloy <jon.maloy@ericsson.com>
M: Allan Stephens <allan.stephens@windriver.com>
F: drivers/cdrom/cdrom.c
F: include/linux/cdrom.h
+UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER
+M: Vinayak Holikatti <vinholikatti@gmail.com>
+M: Santosh Y <santoshsy@gmail.com>
+L: linux-scsi@vger.kernel.org
+S: Supported
+F: Documentation/scsi/ufs.txt
+F: drivers/scsi/ufs/
+
UNSORTED BLOCK IMAGES (UBI)
M: Artem Bityutskiy <dedekind1@gmail.com>
W: http://www.linux-mtd.infradead.org/
S: Maintained
F: drivers/net/usb/pegasus.*
+USB PHY LAYER
+M: Felipe Balbi <balbi@ti.com>
+L: linux-usb@vger.kernel.org
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
+S: Maintained
+F: drivers/usb/phy/
+F: drivers/usb/otg/
+
USB PRINTER DRIVER (usblp)
M: Pete Zaitcev <zaitcev@redhat.com>
L: linux-usb@vger.kernel.org
F: drivers/vlynq/vlynq.c
F: include/linux/vlynq.h
+VME SUBSYSTEM
+M: Martyn Welch <martyn.welch@ge.com>
+M: Manohar Vanga <manohar.vanga@cern.ch>
+M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+L: devel@driverdev.osuosl.org
+S: Maintained
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
+F: Documentation/vme_api.txt
+F: drivers/staging/vme/
+F: drivers/vme/
+F: include/linux/vme*
+
VMWARE VMXNET3 ETHERNET DRIVER
M: Shreyas Bhatewara <sbhatewara@vmware.com>
M: "VMware, Inc." <pv-drivers@vmware.com>
S: Maintained
F: drivers/input/misc/wistron_btns.c
-WL1251 WIRELESS DRIVER
-M: Luciano Coelho <coelho@ti.com>
-L: linux-wireless@vger.kernel.org
-W: http://wireless.kernel.org/en/users/Drivers/wl1251
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git
-S: Maintained
-F: drivers/net/wireless/wl1251/*
-
-WL1271 WIRELESS DRIVER
-M: Luciano Coelho <coelho@ti.com>
-L: linux-wireless@vger.kernel.org
-W: http://wireless.kernel.org/en/users/Drivers/wl12xx
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/luca/wl12xx.git
-S: Maintained
-F: drivers/net/wireless/wl12xx/
-F: include/linux/wl12xx.h
-
WL3501 WIRELESS PCMCIA CARD DRIVER
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
L: linux-wireless@vger.kernel.org
WOLFSON MICROELECTRONICS DRIVERS
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
-M: Ian Lartey <ian@opensource.wolfsonmicro.com>
-M: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+L: patches@opensource.wolfsonmicro.com
T: git git://opensource.wolfsonmicro.com/linux-2.6-asoc
T: git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
F: fs/xfs/
XILINX AXI ETHERNET DRIVER
-M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
-M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
+M: Anirudha Sarangi <anirudh@xilinx.com>
+M: John Linn <John.Linn@xilinx.com>
S: Maintained
F: drivers/net/ethernet/xilinx/xilinx_axienet*
VERSION = 3
PATCHLEVEL = 4
SUBLEVEL = 0
-EXTRAVERSION = -rc2
+EXTRAVERSION =
NAME = Saber-toothed Squirrel
# *DOCUMENTATION*
# Files to ignore in find ... statements
- RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS -o -name .pc -o -name .hg -o -name .git \) -prune -o
- export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn --exclude CVS --exclude .pc --exclude .hg --exclude .git
+ RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \
+ -o -name .pc -o -name .hg -o -name .git \) -prune -o
+ export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
+ --exclude CVS --exclude .pc --exclude .hg --exclude .git
# ===========================================================================
# Rules shared between *config targets and build targets
no-dot-config-targets := clean mrproper distclean \
cscope gtags TAGS tags help %docs check% coccicheck \
- include/linux/version.h headers_% archheaders \
+ include/linux/version.h headers_% archheaders archscripts \
kernelversion %src-pkg
config-targets := 0
ifneq ($(KBUILD_SRC),)
@$(kecho) ' Using $(srctree) as source for kernel'
$(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \
- echo " $(srctree) is not clean, please run 'make mrproper'";\
+ echo " $(srctree) is not clean, please run 'make mrproper'"; \
echo " in the '$(srctree)' directory.";\
/bin/false; \
fi;
include/config/auto.conf
$(cmd_crmodverdir)
-archprepare: archheaders prepare1 scripts_basic
+archprepare: archheaders archscripts prepare1 scripts_basic
prepare0: archprepare FORCE
$(Q)$(MAKE) $(build)=.
endef
define filechk_version.h
- (echo \#define LINUX_VERSION_CODE $(shell \
- expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 0$(SUBLEVEL)); \
+ (echo \#define LINUX_VERSION_CODE $(shell \
+ expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 0$(SUBLEVEL)); \
echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))';)
endef
PHONY += archheaders
archheaders:
+PHONY += archscripts
+archscripts:
+
PHONY += __headers
-__headers: include/linux/version.h scripts_basic asm-generic archheaders FORCE
+__headers: include/linux/version.h scripts_basic asm-generic archheaders archscripts FORCE
$(Q)$(MAKE) $(build)=scripts build_unifdef
PHONY += headers_install_all
kernelversion:
@echo $(KERNELVERSION)
+# Clear a bunch of variables before executing the submake
+tools/: FORCE
+ $(Q)$(MAKE) LDFLAGS= MAKEFLAGS= -C $(src)/tools/
+
+tools/%: FORCE
+ $(Q)$(MAKE) LDFLAGS= MAKEFLAGS= -C $(src)/tools/ $*
+
# Single targets
# ---------------------------------------------------------------------------
# Single targets are compatible with:
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
select HAVE_ARCH_KGDB
+ select HAVE_ARCH_TRACEHOOK
select HAVE_KPROBES if !XIP_KERNEL
select HAVE_KRETPROBES if (HAVE_KPROBES)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
select HAVE_C_RECORDMCOUNT
select HAVE_GENERIC_HARDIRQS
+ select HARDIRQS_SW_RESEND
+ select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
+ select GENERIC_IRQ_PROBE
+ select HARDIRQS_SW_RESEND
select CPU_PM if (SUSPEND || CPU_IDLE)
select GENERIC_PCI_IOMAP
- select HAVE_BPF_JIT if NET
+ select HAVE_BPF_JIT
+ select GENERIC_SMP_IDLE_THREAD
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
bool
default y
-config HARDIRQS_SW_RESEND
- bool
- default y
-
-config GENERIC_IRQ_PROBE
- bool
- default y
-
config GENERIC_LOCKBREAK
bool
default y
and that the relevant menu configurations are displayed for
it.
-config ARCH_HAS_CPU_IDLE_WAIT
- def_bool y
-
config GENERIC_HWEIGHT
bool
default y
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
+ select MULTI_IRQ_HANDLER
help
Support for ARM's Integrator platform.
select IRQ_DOMAIN
select NEED_MACH_IO_H if PCCARD
help
- This enables support for systems based on the Atmel AT91RM9200,
- AT91SAM9 processors.
+ This enables support for systems based on Atmel
+ AT91RM9200 and AT91SAM9* processors.
config ARCH_BCMRING
bool "Broadcom BCMRING"
Support for the Calxeda Highbank SoC based boards.
config ARCH_CLPS711X
- bool "Cirrus Logic CLPS711x/EP721x-based"
+ bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select CPU_ARM720T
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_MEMORY_H
help
- Support for Cirrus Logic 711x/721x based boards.
+ Support for Cirrus Logic 711x/721x/731x based boards.
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
select CLKDEV_LOOKUP
select GENERIC_IRQ_CHIP
select MIGHT_HAVE_CACHE_L2X0
+ select PINCTRL
+ select PINCTRL_SIRF
select USE_OF
select ZONE_DMA
help
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select HAVE_CLK_PREPARE
+ select PINCTRL
help
Support for Freescale MXS-based family of processors
help
Support for Intel's IOP33X (XScale) family of processors.
-config ARCH_IXP23XX
- bool "IXP23XX-based"
- depends on MMU
- select CPU_XSC3
- select PCI
- select ARCH_USES_GETTIMEOFFSET
- select NEED_MACH_IO_H
- select NEED_MACH_MEMORY_H
- help
- Support for Intel's IXP23xx (XScale) family of processors.
-
-config ARCH_IXP2000
- bool "IXP2400/2800-based"
- depends on MMU
- select CPU_XSCALE
- select PCI
- select ARCH_USES_GETTIMEOFFSET
- select NEED_MACH_IO_H
- select NEED_MACH_MEMORY_H
- help
- Support for Intel's IXP2400/2800 (XScale) family of processors.
-
config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
select USB_ARCH_HAS_OHCI
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
+ select USE_OF
help
Support for the NXP LPC32XX family of processors
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select GPIO_PXA
- select TICK_ONESHOT
+ select IRQ_DOMAIN
select PLAT_PXA
select SPARSE_IRQ
select GENERIC_ALLOCATOR
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select GPIO_PXA
- select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
select AUTO_ZRELADDR
select CPU_FREQ
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
- select TICK_ONESHOT
select ARCH_REQUIRE_GPIOLIB
select HAVE_IDE
select NEED_MACH_MEMORY_H
select CPU_ARM926T
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
+ select PINCTRL
select MIGHT_HAVE_CACHE_L2X0
select ARCH_REQUIRE_GPIOLIB
help
source "arch/arm/mach-ixp4xx/Kconfig"
-source "arch/arm/mach-ixp2000/Kconfig"
-
-source "arch/arm/mach-ixp23xx/Kconfig"
-
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/Kconfig-nommu"
endif
+config ARM_ERRATA_326103
+ bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
+ depends on CPU_V6
+ help
+ Executing a SWP instruction to read-only memory does not set bit 11
+ of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
+ treat the access as a read, preventing a COW from occurring and
+ causing the faulting task to livelock.
+
config ARM_ERRATA_411920
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
depends on CPU_V6 || CPU_V6K
help
This option enables support for the ARM system coherency unit
+config ARM_ARCH_TIMER
+ bool "Architected timer support"
+ depends on CPU_V7
+ help
+ This option enables support for the ARM architected timer
+
config HAVE_ARM_TWD
bool
depends on SMP
- select TICK_ONESHOT
help
This options enables support for the ARM timer and watchdog unit
default ZBOOT_ROM_NONE
help
Include experimental SD/MMC loading code in the ROM-able zImage.
- With this enabled it is possible to write the the ROM-able zImage
+ With this enabled it is possible to write the ROM-able zImage
kernel image to an MMC or SD card and boot the kernel straight
from the reset vector. At reset the processor Mask ROM will load
- the first part of the the ROM-able zImage which in turn loads the
+ the first part of the ROM-able zImage which in turn loads the
rest the kernel image to RAM.
config ZBOOT_ROM_NONE
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
- depends on !ARCH_S5PC100
+ depends on !ARCH_S5PC100 && !ARCH_TEGRA
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
- CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
+ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
def_bool y
config ARM_CPU_SUSPEND
select GENERIC_IRQ_PROBE
select IRQ_PER_CPU if SMP
select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
+ select GENERIC_SMP_IDLE_THREAD
config GENERIC_CSUM
def_bool y
help
BF561 Processor Support.
+config BF609
+ bool "BF609"
+ select CLKDEV_LOOKUP
+ help
+ BF609 Processor Support.
+
endchoice
config SMP
config BF_REV_MIN
int
- default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
+ default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
default 2 if (BF537 || BF536 || BF534)
default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
default 4 if (BF538 || BF539)
config BF_REV_MAX
int
- default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
+ default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
default 3 if (BF537 || BF536 || BF534 || BF54xM)
default 5 if (BF561 || BF538 || BF539)
default 6 if (BF533 || BF532 || BF531)
choice
prompt "Silicon Rev"
- default BF_REV_0_0 if (BF51x || BF52x)
+ default BF_REV_0_0 if (BF51x || BF52x || BF60x)
default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
config BF_REV_0_0
bool "0.0"
- depends on (BF51x || BF52x || (BF54x && !BF54xM))
+ depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
config BF_REV_0_1
bool "0.1"
source "arch/blackfin/mach-bf537/Kconfig"
source "arch/blackfin/mach-bf538/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
+source "arch/blackfin/mach-bf609/Kconfig"
menu "Board customizations"
memory region is used to capture NULL pointer references as well
as some core kernel functions.
+config PHY_RAM_BASE_ADDRESS
+ hex "Physical RAM Base"
+ default 0x0
+ help
+ set BF609 FPGA physical SRAM base address
+
config ROM_BASE
hex "Kernel ROM Base"
depends on ROMKERNEL
config PLL_BYPASS
bool "Bypass PLL"
- depends on BFIN_KERNEL_CLOCK
+ depends on BFIN_KERNEL_CLOCK && (!BF60x)
default n
config CLKIN_HALF
default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
- default "20" if BFIN561_EZKIT
+ default "20" if (BFIN561_EZKIT || BF609)
default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
default "25" if BFIN527_AD7160EVAL
help
int "System Clock Divider"
depends on BFIN_KERNEL_CLOCK
range 1 15
- default 5
+ default 4
help
- This sets the frequency of the system clock (including SDRAM or DDR).
+ This sets the frequency of the system clock (including SDRAM or DDR) on
+ !BF60x else it set the clock for system buses and provides the
+ source from which SCLK0 and SCLK1 are derived.
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
+config SCLK0_DIV
+ int "System Clock0 Divider"
+ depends on BFIN_KERNEL_CLOCK && BF60x
+ range 1 15
+ default 1
+ help
+ This sets the frequency of the system clock0 for PVP and all other
+ peripherals not clocked by SCLK1.
+ This can be between 1 and 15
+ System Clock0 = (System Clock) / (this setting)
+
+config SCLK1_DIV
+ int "System Clock1 Divider"
+ depends on BFIN_KERNEL_CLOCK && BF60x
+ range 1 15
+ default 1
+ help
+ This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
+ This can be between 1 and 15
+ System Clock1 = (System Clock) / (this setting)
+
+config DCLK_DIV
+ int "DDR Clock Divider"
+ depends on BFIN_KERNEL_CLOCK && BF60x
+ range 1 15
+ default 2
+ help
+ This sets the frequency of the DDR memory.
+ This can be between 1 and 15
+ DDR Clock = (PLL frequency) / (this setting)
+
choice
prompt "DDR SDRAM Chip Type"
depends on BFIN_KERNEL_CLOCK
choice
prompt "DDR/SDRAM Timing"
- depends on BFIN_KERNEL_CLOCK
+ depends on BFIN_KERNEL_CLOCK && !BF60x
default BFIN_KERNEL_CLOCK_MEMINIT_CALC
help
This option allows you to specify Blackfin SDRAM/DDR Timing parameters
default 600000000 if BF548
default 533333333 if BF549
default 600000000 if BF561
+ default 800000000 if BF609
config MIN_VCO_HZ
int
config MAX_SCLK_HZ
int
+ default 200000000 if BF609
default 133333333
config MIN_SCLK_HZ
config BFIN_L2_DCACHEABLE
bool "Enable DCACHE for L2 SRAM"
depends on BFIN_DCACHE
- depends on (BF54x || BF561) && !SMP
+ depends on (BF54x || BF561 || BF60x) && !SMP
default n
choice
prompt "L2 SRAM DCACHE policy"
comment "Asynchronous Memory Configuration"
menu "EBIU_AMGCTL Global Control"
+ depends on !BF60x
config C_AMCKEN
bool "Enable CLKOUT"
default y
endmenu
menu "EBIU_AMBCTL Control"
+ depends on !BF60x
config BANK_0
hex "Bank 0 (AMBCTL0.L)"
default 0x7BB0
choice
prompt "Standby Power Saving Mode"
- depends on PM
+ depends on PM && !BF60x
default PM_BFIN_SLEEP_DEEPER
config PM_BFIN_SLEEP_DEEPER
bool "Sleep Deeper"
(all processors, except ADSP-BF549). This option sets
the general-purpose wake-up enable (GPWE) control bit to enable
wake-up upon detection of an active low signal on the /GPW (PH7) pin.
- On ADSP-BF549 this option enables the the same functionality on the
+ On ADSP-BF549 this option enables the same functionality on the
/MRXON pin also PH7.
+config PM_BFIN_WAKE_PA15
+ bool "Allow Wake-Up from PA15"
+ depends on PM && BF60x
+ default n
+ help
+ Enable PA15 Wake-Up
+
+config PM_BFIN_WAKE_PA15_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_PA15
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
+config PM_BFIN_WAKE_PB15
+ bool "Allow Wake-Up from PB15"
+ depends on PM && BF60x
+ default n
+ help
+ Enable PB15 Wake-Up
+
+config PM_BFIN_WAKE_PB15_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_PB15
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
+config PM_BFIN_WAKE_PC15
+ bool "Allow Wake-Up from PC15"
+ depends on PM && BF60x
+ default n
+ help
+ Enable PC15 Wake-Up
+
+config PM_BFIN_WAKE_PC15_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_PC15
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
+config PM_BFIN_WAKE_PD06
+ bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
+ depends on PM && BF60x
+ default n
+ help
+ Enable PD06(ETH0_PHYINT) Wake-up
+
+config PM_BFIN_WAKE_PD06_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_PD06
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
+config PM_BFIN_WAKE_PE12
+ bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
+ depends on PM && BF60x
+ default n
+ help
+ Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
+
+config PM_BFIN_WAKE_PE12_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_PE12
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
+config PM_BFIN_WAKE_PG04
+ bool "Allow Wake-Up from PG04(CAN0_RX)"
+ depends on PM && BF60x
+ default n
+ help
+ Enable PG04(CAN0_RX) Wake-up
+
+config PM_BFIN_WAKE_PG04_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_PG04
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
+config PM_BFIN_WAKE_PG13
+ bool "Allow Wake-Up from PG13"
+ depends on PM && BF60x
+ default n
+ help
+ Enable PG13 Wake-Up
+
+config PM_BFIN_WAKE_PG13_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_PG13
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
+config PM_BFIN_WAKE_USB
+ bool "Allow Wake-Up from (USB)"
+ depends on PM && BF60x
+ default n
+ help
+ Enable (USB) Wake-up
+
+config PM_BFIN_WAKE_USB_POL
+ int "Wake-up priority"
+ depends on PM_BFIN_WAKE_USB
+ default 0
+ help
+ Wake-Up priority 0(low) 1(high)
+
endmenu
menu "CPU Frequency scaling"
--- /dev/null
- * Copyright (c) 2006, emlix, Sebastian Hess <sh@emlix.com>
+/***************************************************************************/
+
+/*
+ * linux/arch/m68knommu/platform/532x/config.c
+ *
+ * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ * Copyright (C) 2000, Lineo (www.lineo.com)
+ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
+ * Copyright Freescale Semiconductor, Inc 2006
++ * Copyright (c) 2006, emlix, Sebastian Hess <shess@hessware.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfdma.h>
+#include <asm/mcfgpio.h>
+#include <asm/mcfwdebug.h>
+
+/***************************************************************************/
+
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+ MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+ MCFGPF(FECH, 8, 8),
+ MCFGPF(FECL, 16, 8),
+ MCFGPF(SSI, 24, 5),
+ MCFGPF(BUSCTL, 32, 4),
+ MCFGPF(BE, 40, 4),
+ MCFGPF(CS, 49, 5),
+ MCFGPF(PWM, 58, 4),
+ MCFGPF(FECI2C, 64, 4),
+ MCFGPF(UART, 72, 8),
+ MCFGPF(QSPI, 80, 6),
+ MCFGPF(TIMER, 88, 4),
+ MCFGPF(LCDDATAH, 96, 2),
+ MCFGPF(LCDDATAM, 104, 8),
+ MCFGPF(LCDDATAL, 112, 8),
+ MCFGPF(LCDCTLH, 120, 1),
+ MCFGPF(LCDCTLL, 128, 8),
+};
+
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+
+/***************************************************************************/
+
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
+
+static void __init m532x_qspi_init(void)
+{
+ /* setup QSPS pins for QSPI with gpio CS control */
+ writew(0x01f0, MCF_GPIO_PAR_QSPI);
+}
+
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
+
+/***************************************************************************/
+
+static void __init m532x_uarts_init(void)
+{
+ /* UART GPIO initialization */
+ MCF_GPIO_PAR_UART |= 0x0FFF;
+}
+
+/***************************************************************************/
+
+static void __init m532x_fec_init(void)
+{
+ /* Set multi-function pins to ethernet mode for fec0 */
+ MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
+ MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
+ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
+ MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+#if !defined(CONFIG_BOOTPARAM)
+ /* Copy command line from FLASH to local buffer... */
+ memcpy(commandp, (char *) 0x4000, 4);
+ if(strncmp(commandp, "kcl ", 4) == 0){
+ memcpy(commandp, (char *) 0x4004, size);
+ commandp[size-1] = 0;
+ } else {
+ memset(commandp, 0, size);
+ }
+#endif
+
+ mach_sched_init = hw_timer_init;
+ m532x_uarts_init();
+ m532x_fec_init();
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
+ m532x_qspi_init();
+#endif
+
+#ifdef CONFIG_BDM_DISABLE
+ /*
+ * Disable the BDM clocking. This also turns off most of the rest of
+ * the BDM device. This is good for EMC reasons. This option is not
+ * incompatible with the memory protection option.
+ */
+ wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
+#endif
+}
+
+/***************************************************************************/
+/* Board initialization */
+/***************************************************************************/
+/*
+ * PLL min/max specifications
+ */
+#define MAX_FVCO 500000 /* KHz */
+#define MAX_FSYS 80000 /* KHz */
+#define MIN_FSYS 58333 /* KHz */
+#define FREF 16000 /* KHz */
+
+
+#define MAX_MFD 135 /* Multiplier */
+#define MIN_MFD 88 /* Multiplier */
+#define BUSDIV 6 /* Divider */
+
+/*
+ * Low Power Divider specifications
+ */
+#define MIN_LPD (1 << 0) /* Divider (not encoded) */
+#define MAX_LPD (1 << 15) /* Divider (not encoded) */
+#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
+
+#define SYS_CLK_KHZ 80000
+#define SYSTEM_PERIOD 12.5
+/*
+ * SDRAM Timing Parameters
+ */
+#define SDRAM_BL 8 /* # of beats in a burst */
+#define SDRAM_TWR 2 /* in clocks */
+#define SDRAM_CASL 2.5 /* CASL in clocks */
+#define SDRAM_TRCD 2 /* in clocks */
+#define SDRAM_TRP 2 /* in clocks */
+#define SDRAM_TRFC 7 /* in clocks */
+#define SDRAM_TREFI 7800 /* in ns */
+
+#define EXT_SRAM_ADDRESS (0xC0000000)
+#define FLASH_ADDRESS (0x00000000)
+#define SDRAM_ADDRESS (0x40000000)
+
+#define NAND_FLASH_ADDRESS (0xD0000000)
+
+int sys_clk_khz = 0;
+int sys_clk_mhz = 0;
+
+void wtm_init(void);
+void scm_init(void);
+void gpio_init(void);
+void fbcs_init(void);
+void sdramc_init(void);
+int clock_pll (int fsys, int flags);
+int clock_limp (int);
+int clock_exit_limp (void);
+int get_sys_clock (void);
+
+asmlinkage void __init sysinit(void)
+{
+ sys_clk_khz = clock_pll(0, 0);
+ sys_clk_mhz = sys_clk_khz/1000;
+
+ wtm_init();
+ scm_init();
+ gpio_init();
+ fbcs_init();
+ sdramc_init();
+}
+
+void wtm_init(void)
+{
+ /* Disable watchdog timer */
+ MCF_WTM_WCR = 0;
+}
+
+#define MCF_SCM_BCR_GBW (0x00000100)
+#define MCF_SCM_BCR_GBR (0x00000200)
+
+void scm_init(void)
+{
+ /* All masters are trusted */
+ MCF_SCM_MPR = 0x77777777;
+
+ /* Allow supervisor/user, read/write, and trusted/untrusted
+ access to all slaves */
+ MCF_SCM_PACRA = 0;
+ MCF_SCM_PACRB = 0;
+ MCF_SCM_PACRC = 0;
+ MCF_SCM_PACRD = 0;
+ MCF_SCM_PACRE = 0;
+ MCF_SCM_PACRF = 0;
+
+ /* Enable bursts */
+ MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
+}
+
+
+void fbcs_init(void)
+{
+ MCF_GPIO_PAR_CS = 0x0000003E;
+
+ /* Latch chip select */
+ MCF_FBCS1_CSAR = 0x10080000;
+
+ MCF_FBCS1_CSCR = 0x002A3780;
+ MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
+
+ /* Initialize latch to drive signals to inactive states */
+ *((u16 *)(0x10080000)) = 0xFFFF;
+
+ /* External SRAM */
+ MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
+ MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
+ | MCF_FBCS_CSCR_AA
+ | MCF_FBCS_CSCR_SBM
+ | MCF_FBCS_CSCR_WS(1));
+ MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
+ | MCF_FBCS_CSMR_V);
+
+ /* Boot Flash connected to FBCS0 */
+ MCF_FBCS0_CSAR = FLASH_ADDRESS;
+ MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
+ | MCF_FBCS_CSCR_BEM
+ | MCF_FBCS_CSCR_AA
+ | MCF_FBCS_CSCR_SBM
+ | MCF_FBCS_CSCR_WS(7));
+ MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
+ | MCF_FBCS_CSMR_V);
+}
+
+void sdramc_init(void)
+{
+ /*
+ * Check to see if the SDRAM has already been initialized
+ * by a run control tool
+ */
+ if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
+ /* SDRAM chip select initialization */
+
+ /* Initialize SDRAM chip select */
+ MCF_SDRAMC_SDCS0 = (0
+ | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
+ | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
+
+ /*
+ * Basic configuration and initialization
+ */
+ MCF_SDRAMC_SDCFG1 = (0
+ | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
+ | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
+ | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
+ | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
+ | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
+ | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
+ | MCF_SDRAMC_SDCFG1_WTLAT(3));
+ MCF_SDRAMC_SDCFG2 = (0
+ | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
+ | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
+ | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
+ | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
+
+
+ /*
+ * Precharge and enable write to SDMR
+ */
+ MCF_SDRAMC_SDCR = (0
+ | MCF_SDRAMC_SDCR_MODE_EN
+ | MCF_SDRAMC_SDCR_CKE
+ | MCF_SDRAMC_SDCR_DDR
+ | MCF_SDRAMC_SDCR_MUX(1)
+ | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
+ | MCF_SDRAMC_SDCR_PS_16
+ | MCF_SDRAMC_SDCR_IPALL);
+
+ /*
+ * Write extended mode register
+ */
+ MCF_SDRAMC_SDMR = (0
+ | MCF_SDRAMC_SDMR_BNKAD_LEMR
+ | MCF_SDRAMC_SDMR_AD(0x0)
+ | MCF_SDRAMC_SDMR_CMD);
+
+ /*
+ * Write mode register and reset DLL
+ */
+ MCF_SDRAMC_SDMR = (0
+ | MCF_SDRAMC_SDMR_BNKAD_LMR
+ | MCF_SDRAMC_SDMR_AD(0x163)
+ | MCF_SDRAMC_SDMR_CMD);
+
+ /*
+ * Execute a PALL command
+ */
+ MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
+
+ /*
+ * Perform two REF cycles
+ */
+ MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+ MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+
+ /*
+ * Write mode register and clear reset DLL
+ */
+ MCF_SDRAMC_SDMR = (0
+ | MCF_SDRAMC_SDMR_BNKAD_LMR
+ | MCF_SDRAMC_SDMR_AD(0x063)
+ | MCF_SDRAMC_SDMR_CMD);
+
+ /*
+ * Enable auto refresh and lock SDMR
+ */
+ MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
+ MCF_SDRAMC_SDCR |= (0
+ | MCF_SDRAMC_SDCR_REF
+ | MCF_SDRAMC_SDCR_DQS_OE(0xC));
+ }
+}
+
+void gpio_init(void)
+{
+ /* Enable UART0 pins */
+ MCF_GPIO_PAR_UART = ( 0
+ | MCF_GPIO_PAR_UART_PAR_URXD0
+ | MCF_GPIO_PAR_UART_PAR_UTXD0);
+
+ /* Initialize TIN3 as a GPIO output to enable the write
+ half of the latch */
+ MCF_GPIO_PAR_TIMER = 0x00;
+ __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
+ __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
+
+}
+
+int clock_pll(int fsys, int flags)
+{
+ int fref, temp, fout, mfd;
+ u32 i;
+
+ fref = FREF;
+
+ if (fsys == 0) {
+ /* Return current PLL output */
+ mfd = MCF_PLL_PFDR;
+
+ return (fref * mfd / (BUSDIV * 4));
+ }
+
+ /* Check bounds of requested system clock */
+ if (fsys > MAX_FSYS)
+ fsys = MAX_FSYS;
+ if (fsys < MIN_FSYS)
+ fsys = MIN_FSYS;
+
+ /* Multiplying by 100 when calculating the temp value,
+ and then dividing by 100 to calculate the mfd allows
+ for exact values without needing to include floating
+ point libraries. */
+ temp = 100 * fsys / fref;
+ mfd = 4 * BUSDIV * temp / 100;
+
+ /* Determine the output frequency for selected values */
+ fout = (fref * mfd / (BUSDIV * 4));
+
+ /*
+ * Check to see if the SDRAM has already been initialized.
+ * If it has then the SDRAM needs to be put into self refresh
+ * mode before reprogramming the PLL.
+ */
+ if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+ /* Put SDRAM into self refresh mode */
+ MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
+
+ /*
+ * Initialize the PLL to generate the new system clock frequency.
+ * The device must be put into LIMP mode to reprogram the PLL.
+ */
+
+ /* Enter LIMP mode */
+ clock_limp(DEFAULT_LPD);
+
+ /* Reprogram PLL for desired fsys */
+ MCF_PLL_PODR = (0
+ | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
+ | MCF_PLL_PODR_BUSDIV(BUSDIV));
+
+ MCF_PLL_PFDR = mfd;
+
+ /* Exit LIMP mode */
+ clock_exit_limp();
+
+ /*
+ * Return the SDRAM to normal operation if it is in use.
+ */
+ if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+ /* Exit self refresh mode */
+ MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
+
+ /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
+ MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
+
+ /* wait for DQS logic to relock */
+ for (i = 0; i < 0x200; i++)
+ ;
+
+ return fout;
+}
+
+int clock_limp(int div)
+{
+ u32 temp;
+
+ /* Check bounds of divider */
+ if (div < MIN_LPD)
+ div = MIN_LPD;
+ if (div > MAX_LPD)
+ div = MAX_LPD;
+
+ /* Save of the current value of the SSIDIV so we don't
+ overwrite the value*/
+ temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
+
+ /* Apply the divider to the system clock */
+ MCF_CCM_CDR = ( 0
+ | MCF_CCM_CDR_LPDIV(div)
+ | MCF_CCM_CDR_SSIDIV(temp));
+
+ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
+
+ return (FREF/(3*(1 << div)));
+}
+
+int clock_exit_limp(void)
+{
+ int fout;
+
+ /* Exit LIMP mode */
+ MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
+
+ /* Wait for PLL to lock */
+ while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
+ ;
+
+ fout = get_sys_clock();
+
+ return fout;
+}
+
+int get_sys_clock(void)
+{
+ int divider;
+
+ /* Test to see if device is in LIMP mode */
+ if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
+ divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
+ return (FREF/(2 << divider));
+ }
+ else
+ return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
+}
select HAVE_MEMBLOCK
select HAVE_MEMBLOCK_NODE_MAP
select ARCH_DISCARD_MEMBLOCK
+ select GENERIC_SMP_IDLE_THREAD
menu "Machine selection"
bool
#
- # Endianess selection. Sufficiently obscure so many users don't know what to
+ # Endianness selection. Sufficiently obscure so many users don't know what to
# answer,so we try hard to limit the available choices. Also the use of a
# choice statement should be more obvious to the user.
#
choice
- prompt "Endianess selection"
+ prompt "Endianness selection"
help
Some MIPS machines can be configured for either little or big endian
byte order. These modes require different kernels and a different
def_bool y
select OF
select OF_EARLY_FLATTREE
+ select IRQ_DOMAIN
select HAVE_MEMBLOCK
select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_ARCH_TRACEHOOK
bool "Check for kernel stack overflow"
default y
help
- Make extra checks for space avaliable on stack in some
+ Make extra checks for space available on stack in some
critical functions. This will cause kernel to run a bit slower,
but will catch most of kernel stack overruns and exit gracefuly.
two or more partitions.
config EEH
- bool "PCI Extended Error Handling (EEH)" if EXPERT
+ bool
depends on PPC_PSERIES && PCI
- default y if !EXPERT
+ default y
config PSERIES_MSI
bool
This option will only enable the IO event platform code. You
will still need to enable or compile the actual drivers
- that use this infrastruture to handle IO event interrupts.
+ that use this infrastructure to handle IO event interrupts.
Say Y if you are unsure.
If unsure, say Y.
config HID_BATTERY_STRENGTH
- bool
+ bool "Battery level reporting for HID devices"
depends on HID && POWER_SUPPLY && HID = POWER_SUPPLY
- default y
+ default n
+ ---help---
+ This option adds support of reporting battery strength (for HID devices
+ that support this feature) through power_supply class so that userspace
+ tools, such as upower, can display it.
config HIDRAW
bool "/dev/hidraw raw HID device support"
menu "Special HID drivers"
depends on HID
+config HID_GENERIC
+ tristate "Generic HID driver"
+ depends on HID
+ default y
+ ---help---
+ Support for generic HID devices.
+
+ To compile this driver as a module, choose M here: the module
+ will be called hid-generic.
+
+ If unsure, say Y.
+
config HID_A4TECH
tristate "A4 tech mice" if EXPERT
depends on USB_HID
Say Y here if you want support for keyboards of Apple iBooks, PowerBooks,
MacBooks, MacBook Pros and Apple Aluminum.
+config HID_AUREAL
+ tristate "Aureal"
+ depends on USB_HID
+ ---help---
+ Support for Aureal Cy se W-01RN Remote Controller and other Aureal derived remotes.
+
config HID_BELKIN
tristate "Belkin Flip KVM and Wireless keyboard" if EXPERT
depends on USB_HID
select FB_SYS_FOPS
---help---
Provide access to PicoLCD's 256x64 monochrome display via a
- frambuffer device.
+ framebuffer device.
config HID_PICOLCD_BACKLIGHT
bool "Backlight control" if EXPERT
config HID_WACOM
tristate "Wacom Bluetooth devices support"
depends on BT_HIDP
- ---help---
- Support for Wacom Graphire Bluetooth tablet.
-
-config HID_WACOM_POWER_SUPPLY
- bool "Wacom Bluetooth devices power supply status support"
- depends on HID_WACOM
+ depends on LEDS_CLASS
select POWER_SUPPLY
---help---
- Say Y here if you want to enable power supply status monitoring for
- Wacom Bluetooth devices.
+ Support for Wacom Graphire Bluetooth and Intuos4 WL tablets.
config HID_WIIMOTE
tristate "Nintendo Wii Remote support"
bool "TPS6586x Power Management chips"
depends on I2C=y && GPIOLIB && GENERIC_HARDIRQS
select MFD_CORE
+ depends on REGULATOR
help
If you say yes here you get support for the TPS6586X series of
Power Management chips.
This is used to control charging LED brightness.
config TWL6040_CORE
- bool
- depends on TWL4030_CORE && GENERIC_HARDIRQS
+ bool "Support for TWL6040 audio codec"
+ depends on I2C=y && GENERIC_HARDIRQS
select MFD_CORE
+ select REGMAP_I2C
default n
+ help
+ Say yes here if you want support for Texas Instruments TWL6040 audio
+ codec.
+ This driver provides common support for accessing the device,
+ additional drivers must be enabled in order to use the
+ functionality of the device (audio, vibra).
config MFD_STMPE
bool "Support STMicroelectronics STMPE"
config MFD_DA9052_SPI
bool "Support Dialog Semiconductor DA9052/53 PMIC variants with SPI"
+ select IRQ_DOMAIN
select REGMAP_SPI
select REGMAP_IRQ
select PMIC_DA9052
config MFD_DA9052_I2C
bool "Support Dialog Semiconductor DA9052/53 PMIC variants with I2C"
+ select IRQ_DOMAIN
select REGMAP_I2C
select REGMAP_IRQ
select PMIC_DA9052
select MFD_CORE
help
Say yes here to support for Maxim Semiconductor MAX8925. This is
- a Power Management IC. This driver provies common support for
+ a Power Management IC. This driver provides common support for
accessing the device, additional drivers must be enabled in order
to use the functionality of the device.
help
Say yes here to support for Maxim Semiconductor MAX8998 and
National Semiconductor LP3974. This is a Power Management IC.
- This driver provies common support for accessing the device,
+ This driver provides common support for accessing the device,
additional drivers must be enabled in order to use the functionality
of the device.
select REGMAP_I2C
help
Support for the Samsung Electronics S5M MFD series.
- This driver provies common support for accessing the device,
+ This driver provides common support for accessing the device,
additional drivers must be enabled in order to use the functionality
of the device
bool "Support Wolfson Microelectronics WM8994"
select MFD_CORE
select REGMAP_I2C
+ select IRQ_DOMAIN
select REGMAP_IRQ
depends on I2C=y && GENERIC_HARDIRQS
help
This enables the PCAP ASIC present on EZX Phones. This is
needed for MMC, TouchScreen, Sound, USB, etc..
-config AB5500_CORE
- bool "ST-Ericsson AB5500 Mixed Signal Power Management chip"
- depends on ABX500_CORE && MFD_DB5500_PRCMU
- select MFD_CORE
- help
- Select this option to enable access to AB5500 power management
- chip. This connects to the db5500 chip via the I2C bus via PRCMU.
- This chip embeds various other multimedia funtionalities as well.
-
-config AB5500_DEBUG
- bool "Enable debug info via debugfs"
- depends on AB5500_CORE && DEBUG_FS
- default y if DEBUG_FS
- help
- Select this option if you want debug information from the AB5500
- using the debug filesystem, debugfs.
-
config AB8500_CORE
bool "ST-Ericsson AB8500 Mixed Signal Power Management chip"
depends on GENERIC_HARDIRQS && ABX500_CORE
system controller running an XP70 microprocessor, which is accessed
through a register map.
-config MFD_DB5500_PRCMU
- bool "ST-Ericsson DB5500 Power Reset Control Management Unit"
- depends on UX500_SOC_DB5500
- select MFD_CORE
- help
- Select this option to enable support for the DB5500 Power Reset
- and Control Management Unit. This is basically an autonomous
- system controller running an XP70 microprocessor, which is accessed
- through a register map.
-
config MFD_CS5535
tristate "Support for CS5535 and CS5536 southbridge core functions"
select MFD_CORE
MFD controller. This controller embeds regulator and
thermal devices for Freescale i.MX platforms.
+config MFD_PALMAS
+ bool "Support for the TI Palmas series chips"
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ depends on I2C=y
+ help
+ If you say yes here you get support for the Palmas
+ series of PMIC chips from Texas Instruments.
+
endmenu
endif
if (sblk->status & SD_STATUS_LINK_CHG)
work_exists = 1;
}
- /* check for RX/TX work to do */
- if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
+
+ /* check for TX work to do */
+ if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
+ work_exists = 1;
+
+ /* check for RX work to do */
+ if (tnapi->rx_rcb_prod_idx &&
*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
work_exists = 1;
}
}
+static void tg3_frag_free(bool is_frag, void *data)
+{
+ if (is_frag)
+ put_page(virt_to_head_page(data));
+ else
+ kfree(data);
+}
+
static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
{
+ unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
+
if (!ri->data)
return;
pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
map_sz, PCI_DMA_FROMDEVICE);
- kfree(ri->data);
+ tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
ri->data = NULL;
}
+
/* Returns size of skb allocated or < 0 on error.
*
* We only need to fill in the address because the other members
* (to fetch the error flags, vlan tag, checksum, and opaque cookie).
*/
static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
- u32 opaque_key, u32 dest_idx_unmasked)
+ u32 opaque_key, u32 dest_idx_unmasked,
+ unsigned int *frag_size)
{
struct tg3_rx_buffer_desc *desc;
struct ring_info *map;
*/
skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- data = kmalloc(skb_size, GFP_ATOMIC);
+ if (skb_size <= PAGE_SIZE) {
+ data = netdev_alloc_frag(skb_size);
+ *frag_size = skb_size;
+ } else {
+ data = kmalloc(skb_size, GFP_ATOMIC);
+ *frag_size = 0;
+ }
if (!data)
return -ENOMEM;
data + TG3_RX_OFFSET(tp),
data_size,
PCI_DMA_FROMDEVICE);
- if (pci_dma_mapping_error(tp->pdev, mapping)) {
- kfree(data);
+ if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
+ tg3_frag_free(skb_size <= PAGE_SIZE, data);
return -EIO;
}
if (len > TG3_RX_COPY_THRESH(tp)) {
int skb_size;
+ unsigned int frag_size;
skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
- *post_ptr);
+ *post_ptr, &frag_size);
if (skb_size < 0)
goto drop_it;
pci_unmap_single(tp->pdev, dma_addr, skb_size,
PCI_DMA_FROMDEVICE);
- skb = build_skb(data);
+ skb = build_skb(data, frag_size);
if (!skb) {
- kfree(data);
+ tg3_frag_free(frag_size != 0, data);
goto drop_it_no_recycle;
}
skb_reserve(skb, TG3_RX_OFFSET(tp));
return work_done;
}
+ if (!tnapi->rx_rcb_prod_idx)
+ return work_done;
+
/* run RX thread, within the bounds set by NAPI.
* All RX "locking" is done by ensuring outside
* code synchronizes with tg3->napi.poll()
/* Now allocate fresh SKBs for each rx ring. */
for (i = 0; i < tp->rx_pending; i++) {
- if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
+ unsigned int frag_size;
+
+ if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
+ &frag_size) < 0) {
netdev_warn(tp->dev,
"Using a smaller RX standard ring. Only "
"%d out of %d buffers were allocated "
}
for (i = 0; i < tp->rx_jumbo_pending; i++) {
- if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
+ unsigned int frag_size;
+
+ if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
+ &frag_size) < 0) {
netdev_warn(tp->dev,
"Using a smaller RX jumbo ring. Only %d "
"out of %d buffers were allocated "
*/
switch (i) {
default:
+ if (tg3_flag(tp, ENABLE_RSS)) {
+ tnapi->rx_rcb_prod_idx = NULL;
+ break;
+ }
+ /* Fall through */
+ case 1:
tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
break;
case 2:
.get_rxfh_indir_size = tg3_get_rxfh_indir_size,
.get_rxfh_indir = tg3_get_rxfh_indir,
.set_rxfh_indir = tg3_set_rxfh_indir,
+ .get_ts_info = ethtool_op_get_ts_info,
};
static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
if (dev) {
struct tg3 *tp = netdev_priv(dev);
- if (tp->fw)
- release_firmware(tp->fw);
+ release_firmware(tp->fw);
tg3_reset_task_cancel(tp);
(sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
} while (0)
-#define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
-
static void
bnad_add_to_list(struct bnad *bnad)
{
* Reinitialize completions in CQ, once Rx is taken down
*/
static void
-bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
+bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
{
struct bna_cq_entry *cmpl, *next_cmpl;
unsigned int wi_range, wis = 0, ccb_prod = 0;
for (j = 0; j < frag; j++) {
dma_unmap_page(pdev, dma_unmap_addr(&array[index], dma_addr),
- skb_frag_size(&skb_shinfo(skb)->frags[j]), DMA_TO_DEVICE);
+ skb_frag_size(&skb_shinfo(skb)->frags[j]),
+ DMA_TO_DEVICE);
dma_unmap_addr_set(&array[index], dma_addr, 0);
BNA_QE_INDX_ADD(index, 1, depth);
}
* so DMA unmap & freeing is fine.
*/
static void
-bnad_free_all_txbufs(struct bnad *bnad,
+bnad_txq_cleanup(struct bnad *bnad,
struct bna_tcb *tcb)
{
u32 unmap_cons;
/* Data Path Handlers */
/*
- * bnad_free_txbufs : Frees the Tx bufs on Tx completion
+ * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
* Can be called in a) Interrupt context
* b) Sending context
- * c) Tasklet context
*/
static u32
-bnad_free_txbufs(struct bnad *bnad,
+bnad_txcmpl_process(struct bnad *bnad,
struct bna_tcb *tcb)
{
u32 unmap_cons, sent_packets = 0, sent_bytes = 0;
struct bnad_skb_unmap *unmap_array;
struct sk_buff *skb;
- /*
- * Just return if TX is stopped. This check is useful
- * when bnad_free_txbufs() runs out of a tasklet scheduled
- * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
- * but this routine runs actually after the cleanup has been
- * executed.
- */
+ /* Just return if TX is stopped */
if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
return 0;
return sent_packets;
}
-/* Tx Free Tasklet function */
-/* Frees for all the tcb's in all the Tx's */
-/*
- * Scheduled from sending context, so that
- * the fat Tx lock is not held for too long
- * in the sending context.
- */
-static void
-bnad_tx_free_tasklet(unsigned long bnad_ptr)
-{
- struct bnad *bnad = (struct bnad *)bnad_ptr;
- struct bna_tcb *tcb;
- u32 acked = 0;
- int i, j;
-
- for (i = 0; i < bnad->num_tx; i++) {
- for (j = 0; j < bnad->num_txq_per_tx; j++) {
- tcb = bnad->tx_info[i].tcb[j];
- if (!tcb)
- continue;
- if (((u16) (*tcb->hw_consumer_index) !=
- tcb->consumer_index) &&
- (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
- &tcb->flags))) {
- acked = bnad_free_txbufs(bnad, tcb);
- if (likely(test_bit(BNAD_TXQ_TX_STARTED,
- &tcb->flags)))
- bna_ib_ack(tcb->i_dbell, acked);
- smp_mb__before_clear_bit();
- clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
- }
- if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
- &tcb->flags)))
- continue;
- if (netif_queue_stopped(bnad->netdev)) {
- if (acked && netif_carrier_ok(bnad->netdev) &&
- BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
- BNAD_NETIF_WAKE_THRESHOLD) {
- netif_wake_queue(bnad->netdev);
- /* TODO */
- /* Counters for individual TxQs? */
- BNAD_UPDATE_CTR(bnad,
- netif_queue_wakeup);
- }
- }
- }
- }
-}
-
static u32
-bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
+bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
{
struct net_device *netdev = bnad->netdev;
u32 sent = 0;
if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
return 0;
- sent = bnad_free_txbufs(bnad, tcb);
+ sent = bnad_txcmpl_process(bnad, tcb);
if (sent) {
if (netif_queue_stopped(netdev) &&
netif_carrier_ok(netdev) &&
struct bna_tcb *tcb = (struct bna_tcb *)data;
struct bnad *bnad = tcb->bnad;
- bnad_tx(bnad, tcb);
+ bnad_tx_complete(bnad, tcb);
return IRQ_HANDLED;
}
static void
-bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
+bnad_rcb_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
{
struct bnad_unmap_q *unmap_q = rcb->unmap_q;
}
static void
-bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
+bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
{
struct bnad_unmap_q *unmap_q;
struct bnad_skb_unmap *unmap_array;
DMA_FROM_DEVICE);
dev_kfree_skb(skb);
}
- bnad_reset_rcb(bnad, rcb);
+ bnad_rcb_cleanup(bnad, rcb);
}
static void
-bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
+bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
{
u16 to_alloc, alloced, unmap_prod, wi_range;
struct bnad_unmap_q *unmap_q = rcb->unmap_q;
if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
>> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
- bnad_alloc_n_post_rxbufs(bnad, rcb);
+ bnad_rxq_post(bnad, rcb);
smp_mb__before_clear_bit();
clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
}
}
static u32
-bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
+bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
{
struct bna_cq_entry *cmpl, *next_cmpl;
struct bna_rcb *rcb = NULL;
struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
- set_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
-
- if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)) {
- clear_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
+ if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))
return 0;
- }
prefetch(bnad->netdev);
BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
if (skb->ip_summed == CHECKSUM_UNNECESSARY)
napi_gro_receive(&rx_ctrl->napi, skb);
- else {
+ else
netif_receive_skb(skb);
- }
next:
cmpl->valid = 0;
for (j = 0; j < bnad->num_txq_per_tx; j++) {
tcb = bnad->tx_info[i].tcb[j];
if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
- bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
+ bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
}
}
/* Rx processing */
{
struct bnad_tx_info *tx_info =
(struct bnad_tx_info *)tcb->txq->tx->priv;
- struct bnad_unmap_q *unmap_q = tcb->unmap_q;
-
- while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
- cpu_relax();
-
- bnad_free_all_txbufs(bnad, tcb);
-
- unmap_q->producer_index = 0;
- unmap_q->consumer_index = 0;
-
- smp_mb__before_clear_bit();
- clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
tx_info->tcb[tcb->id] = NULL;
+ tcb->priv = NULL;
}
static void
unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
}
-static void
-bnad_cb_rcb_destroy(struct bnad *bnad, struct bna_rcb *rcb)
-{
- bnad_free_all_rxbufs(bnad, rcb);
-}
-
static void
bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
{
{
struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
struct bna_tcb *tcb;
- struct bnad_unmap_q *unmap_q;
u32 txq_id;
int i;
continue;
txq_id = tcb->id;
- unmap_q = tcb->unmap_q;
-
- if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
- continue;
-
- while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
- cpu_relax();
-
- bnad_free_all_txbufs(bnad, tcb);
-
- unmap_q->producer_index = 0;
- unmap_q->consumer_index = 0;
-
- smp_mb__before_clear_bit();
- clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
-
+ BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
+ BUG_ON(*(tcb->hw_consumer_index) != 0);
if (netif_carrier_ok(bnad->netdev)) {
printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
}
}
+/*
+ * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
+ */
+static void
+bnad_tx_cleanup(struct delayed_work *work)
+{
+ struct bnad_tx_info *tx_info =
+ container_of(work, struct bnad_tx_info, tx_cleanup_work);
+ struct bnad *bnad = NULL;
+ struct bnad_unmap_q *unmap_q;
+ struct bna_tcb *tcb;
+ unsigned long flags;
+ uint32_t i, pending = 0;
+
+ for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
+ tcb = tx_info->tcb[i];
+ if (!tcb)
+ continue;
+
+ bnad = tcb->bnad;
+
+ if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
+ pending++;
+ continue;
+ }
+
+ bnad_txq_cleanup(bnad, tcb);
+
+ unmap_q = tcb->unmap_q;
+ unmap_q->producer_index = 0;
+ unmap_q->consumer_index = 0;
+
+ smp_mb__before_clear_bit();
+ clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
+ }
+
+ if (pending) {
+ queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
+ msecs_to_jiffies(1));
+ return;
+ }
+
+ spin_lock_irqsave(&bnad->bna_lock, flags);
+ bna_tx_cleanup_complete(tx_info->tx);
+ spin_unlock_irqrestore(&bnad->bna_lock, flags);
+}
+
+
static void
bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
{
continue;
}
- mdelay(BNAD_TXRX_SYNC_MDELAY);
- bna_tx_cleanup_complete(tx);
+ queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
}
static void
}
}
+/*
+ * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
+ */
+static void
+bnad_rx_cleanup(void *work)
+{
+ struct bnad_rx_info *rx_info =
+ container_of(work, struct bnad_rx_info, rx_cleanup_work);
+ struct bnad_rx_ctrl *rx_ctrl;
+ struct bnad *bnad = NULL;
+ unsigned long flags;
+ uint32_t i;
+
+ for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
+ rx_ctrl = &rx_info->rx_ctrl[i];
+
+ if (!rx_ctrl->ccb)
+ continue;
+
+ bnad = rx_ctrl->ccb->bnad;
+
+ /*
+ * Wait till the poll handler has exited
+ * and nothing can be scheduled anymore
+ */
+ napi_disable(&rx_ctrl->napi);
+
+ bnad_cq_cleanup(bnad, rx_ctrl->ccb);
+ bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
+ if (rx_ctrl->ccb->rcb[1])
+ bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
+ }
+
+ spin_lock_irqsave(&bnad->bna_lock, flags);
+ bna_rx_cleanup_complete(rx_info->rx);
+ spin_unlock_irqrestore(&bnad->bna_lock, flags);
+}
+
static void
bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
{
struct bnad_rx_ctrl *rx_ctrl;
int i;
- mdelay(BNAD_TXRX_SYNC_MDELAY);
-
for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
rx_ctrl = &rx_info->rx_ctrl[i];
ccb = rx_ctrl->ccb;
if (ccb->rcb[1])
clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
-
- while (test_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags))
- cpu_relax();
}
- bna_rx_cleanup_complete(rx);
+ queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
}
static void
if (!ccb)
continue;
- bnad_cq_cmpl_init(bnad, ccb);
+ napi_enable(&rx_ctrl->napi);
for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
rcb = ccb->rcb[j];
if (!rcb)
continue;
- bnad_free_all_rxbufs(bnad, rcb);
set_bit(BNAD_RXQ_STARTED, &rcb->flags);
set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
>> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
- bnad_alloc_n_post_rxbufs(bnad, rcb);
+ bnad_rxq_post(bnad, rcb);
smp_mb__before_clear_bit();
clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
}
if (!netif_carrier_ok(bnad->netdev))
goto poll_exit;
- rcvd = bnad_poll_cq(bnad, rx_ctrl->ccb, budget);
+ rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
if (rcvd >= budget)
return rcvd;
#define BNAD_NAPI_POLL_QUOTA 64
static void
-bnad_napi_init(struct bnad *bnad, u32 rx_id)
+bnad_napi_add(struct bnad *bnad, u32 rx_id)
{
struct bnad_rx_ctrl *rx_ctrl;
int i;
}
static void
-bnad_napi_enable(struct bnad *bnad, u32 rx_id)
-{
- struct bnad_rx_ctrl *rx_ctrl;
- int i;
-
- /* Initialize & enable NAPI */
- for (i = 0; i < bnad->num_rxp_per_rx; i++) {
- rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
-
- napi_enable(&rx_ctrl->napi);
- }
-}
-
-static void
-bnad_napi_disable(struct bnad *bnad, u32 rx_id)
+bnad_napi_delete(struct bnad *bnad, u32 rx_id)
{
int i;
/* First disable and then clean up */
- for (i = 0; i < bnad->num_rxp_per_rx; i++) {
- napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
+ for (i = 0; i < bnad->num_rxp_per_rx; i++)
netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
- }
}
/* Should be held with conf_lock held */
void
-bnad_cleanup_tx(struct bnad *bnad, u32 tx_id)
+bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
{
struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
bnad_tx_msix_unregister(bnad, tx_info,
bnad->num_txq_per_tx);
- if (0 == tx_id)
- tasklet_kill(&bnad->tx_free_tasklet);
-
spin_lock_irqsave(&bnad->bna_lock, flags);
bna_tx_destroy(tx_info->tx);
spin_unlock_irqrestore(&bnad->bna_lock, flags);
goto err_return;
tx_info->tx = tx;
+ INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
+ (work_func_t)bnad_tx_cleanup);
+
/* Register ISR for the Tx object */
if (intr_info->intr_type == BNA_INTR_T_MSIX) {
err = bnad_tx_msix_register(bnad, tx_info,
/* Called with mutex_lock(&bnad->conf_mutex) held */
void
-bnad_cleanup_rx(struct bnad *bnad, u32 rx_id)
+bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
{
struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
- bnad_napi_disable(bnad, rx_id);
+ bnad_napi_delete(bnad, rx_id);
spin_lock_irqsave(&bnad->bna_lock, flags);
bna_rx_destroy(rx_info->rx);
struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
static const struct bna_rx_event_cbfn rx_cbfn = {
.rcb_setup_cbfn = bnad_cb_rcb_setup,
- .rcb_destroy_cbfn = bnad_cb_rcb_destroy,
+ .rcb_destroy_cbfn = NULL,
.ccb_setup_cbfn = bnad_cb_ccb_setup,
.ccb_destroy_cbfn = bnad_cb_ccb_destroy,
.rx_stall_cbfn = bnad_cb_rx_stall,
rx_info->rx = rx;
spin_unlock_irqrestore(&bnad->bna_lock, flags);
+ INIT_WORK(&rx_info->rx_cleanup_work,
+ (work_func_t)(bnad_rx_cleanup));
+
/*
* Init NAPI, so that state is set to NAPI_STATE_SCHED,
* so that IRQ handler cannot schedule NAPI at this point.
*/
- bnad_napi_init(bnad, rx_id);
+ bnad_napi_add(bnad, rx_id);
/* Register ISR for the Rx object */
if (intr_info->intr_type == BNA_INTR_T_MSIX) {
bna_rx_enable(rx);
spin_unlock_irqrestore(&bnad->bna_lock, flags);
- /* Enable scheduling of NAPI */
- bnad_napi_enable(bnad, rx_id);
-
return 0;
err_return:
- bnad_cleanup_rx(bnad, rx_id);
+ bnad_destroy_rx(bnad, rx_id);
return err;
}
return 0;
cleanup_tx:
- bnad_cleanup_tx(bnad, 0);
+ bnad_destroy_tx(bnad, 0);
err_return:
mutex_unlock(&bnad->conf_mutex);
wait_for_completion(&bnad->bnad_completions.enet_comp);
- bnad_cleanup_tx(bnad, 0);
- bnad_cleanup_rx(bnad, 0);
+ bnad_destroy_tx(bnad, 0);
+ bnad_destroy_rx(bnad, 0);
/* Synchronize mailbox IRQ */
bnad_mbox_irq_sync(bnad);
if ((u16) (*tcb->hw_consumer_index) !=
tcb->consumer_index &&
!test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
- acked = bnad_free_txbufs(bnad, tcb);
+ acked = bnad_txcmpl_process(bnad, tcb);
if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
bna_ib_ack(tcb->i_dbell, acked);
smp_mb__before_clear_bit();
bna_txq_prod_indx_doorbell(tcb);
smp_mb();
- if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
- tasklet_schedule(&bnad->tx_free_tasklet);
-
return NETDEV_TX_OK;
}
/*
* 1. Initialize the bnad structure
* 2. Setup netdev pointer in pci_dev
- * 3. Initialze Tx free tasklet
- * 4. Initialize no. of TxQ & CQs & MSIX vectors
+ * 3. Initialize no. of TxQ & CQs & MSIX vectors
+ * 4. Initialize work queue.
*/
static int
bnad_init(struct bnad *bnad,
bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
- tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
- (unsigned long)bnad);
+ sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
+ bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
+
+ if (!bnad->work_q)
+ return -ENOMEM;
return 0;
}
static void
bnad_uninit(struct bnad *bnad)
{
+ if (bnad->work_q) {
+ flush_workqueue(bnad->work_q);
+ destroy_workqueue(bnad->work_q);
+ bnad->work_q = NULL;
+ }
+
if (bnad->bar0)
iounmap(bnad->bar0);
pci_set_drvdata(bnad->pcidev, NULL);
/*
* Initialize bnad structure
* Setup relation between pci_dev & netdev
- * Init Tx free tasklet
*/
err = bnad_init(bnad, pdev, netdev);
if (err)
bnad_module_exit(void)
{
pci_unregister_driver(&bnad_pci_driver);
-
- if (bfi_fw)
- release_firmware(bfi_fw);
+ release_firmware(bfi_fw);
}
module_init(bnad_module_init);
_build(file_fw_ver));
return -EINVAL;
}
-
val = nx_get_bios_version(adapter);
netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
if ((__force u32)val != bios) {
void
netxen_release_firmware(struct netxen_adapter *adapter)
{
- if (adapter->fw)
- release_firmware(adapter->fw);
+ release_firmware(adapter->fw);
adapter->fw = NULL;
}
length = skb->len;
+ if (adapter->flags & NETXEN_FW_MSS_CAP)
+ skb_shinfo(skb)->gso_size = netxen_get_lro_sts_mss(sts_data1);
+
netif_receive_skb(skb);
adapter->stats.lro_pkts++;
#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
+#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
+#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
#ifdef RTL8169_DEBUG
#define assert(expr) \
#define R8169_MSG_DEFAULT \
(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
-#define TX_BUFFS_AVAIL(tp) \
- (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
+#define TX_SLOTS_AVAIL(tp) \
+ (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
+
+/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
+#define TX_FRAGS_READY_FOR(tp,nr_frags) \
+ (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
The RTL chips use a 64 element hash table based on the Ethernet CRC. */
RTL_GIGA_MAC_VER_34,
RTL_GIGA_MAC_VER_35,
RTL_GIGA_MAC_VER_36,
+ RTL_GIGA_MAC_VER_37,
+ RTL_GIGA_MAC_VER_38,
RTL_GIGA_MAC_NONE = 0xff,
};
[RTL_GIGA_MAC_VER_36] =
_R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
JUMBO_9K, false),
+ [RTL_GIGA_MAC_VER_37] =
+ _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
+ JUMBO_1K, true),
+ [RTL_GIGA_MAC_VER_38] =
+ _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
+ JUMBO_9K, false),
};
#undef _R
Config0 = 0x51,
Config1 = 0x52,
Config2 = 0x53,
+#define PME_SIGNAL (1 << 5) /* 8168c and later */
+
Config3 = 0x54,
Config4 = 0x55,
Config5 = 0x56,
#define CSIAR_BYTE_ENABLE 0x0f
#define CSIAR_BYTE_ENABLE_SHIFT 12
#define CSIAR_ADDR_MASK 0x0fff
+#define CSIAR_FUNC_CARD 0x00000000
+#define CSIAR_FUNC_SDIO 0x00010000
+#define CSIAR_FUNC_NIC 0x00020000
PMCH = 0x6f,
EPHYAR = 0x80,
#define EPHYAR_FLAG 0x80000000
void (*disable)(struct rtl8169_private *);
} jumbo_ops;
+ struct csi_ops {
+ void (*write)(void __iomem *, int, int);
+ u32 (*read)(void __iomem *, int);
+ } csi_ops;
+
int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
int (*get_settings)(struct net_device *, struct ethtool_cmd *);
void (*phy_reset_enable)(struct rtl8169_private *tp);
MODULE_FIRMWARE(FIRMWARE_8105E_1);
MODULE_FIRMWARE(FIRMWARE_8168F_1);
MODULE_FIRMWARE(FIRMWARE_8168F_2);
+MODULE_FIRMWARE(FIRMWARE_8402_1);
+MODULE_FIRMWARE(FIRMWARE_8411_1);
static void rtl_lock_work(struct rtl8169_private *tp)
{
return value;
}
-static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
-{
- unsigned int i;
-
- RTL_W32(CSIDR, value);
- RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
- CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
-
- for (i = 0; i < 100; i++) {
- if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
- break;
- udelay(10);
- }
-}
-
-static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
-{
- u32 value = ~0x00;
- unsigned int i;
-
- RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
- CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
-
- for (i = 0; i < 100; i++) {
- if (RTL_R32(CSIAR) & CSIAR_FLAG) {
- value = RTL_R32(CSIDR);
- break;
- }
- udelay(10);
- }
-
- return value;
-}
-
static
void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
{
if (!netif_running(dev))
return;
- if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
+ if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
+ tp->mac_version == RTL_GIGA_MAC_VER_38) {
if (RTL_R8(PHYstatus) & _1000bpsF) {
rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
0x00000011, ERIAR_EXGMAC);
rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
0x0000003f, ERIAR_EXGMAC);
}
+ } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
+ if (RTL_R8(PHYstatus) & _10bps) {
+ rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
+ 0x4d02, ERIAR_EXGMAC);
+ rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011,
+ 0x0060, ERIAR_EXGMAC);
+ } else {
+ rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
+ 0x0000, ERIAR_EXGMAC);
+ }
}
}
u16 reg;
u8 mask;
} cfg[] = {
- { WAKE_ANY, Config1, PMEnable },
{ WAKE_PHY, Config3, LinkUp },
{ WAKE_MAGIC, Config3, MagicPacket },
{ WAKE_UCAST, Config5, UWF },
{ WAKE_MCAST, Config5, MWF },
{ WAKE_ANY, Config5, LanWake }
};
+ u8 options;
RTL_W8(Cfg9346, Cfg9346_Unlock);
for (i = 0; i < ARRAY_SIZE(cfg); i++) {
- u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
+ options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
if (wolopts & cfg[i].opt)
options |= cfg[i].mask;
RTL_W8(cfg[i].reg, options);
}
+ switch (tp->mac_version) {
+ case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
+ options = RTL_R8(Config1) & ~PMEnable;
+ if (wolopts)
+ options |= PMEnable;
+ RTL_W8(Config1, options);
+ break;
+ default:
+ options = RTL_R8(Config2) & ~PME_SIGNAL;
+ if (wolopts)
+ options |= PME_SIGNAL;
+ RTL_W8(Config2, options);
+ break;
+ }
+
RTL_W8(Cfg9346, Cfg9346_Lock);
}
.get_strings = rtl8169_get_strings,
.get_sset_count = rtl8169_get_sset_count,
.get_ethtool_stats = rtl8169_get_ethtool_stats,
+ .get_ts_info = ethtool_op_get_ts_info,
};
static void rtl8169_get_mac_version(struct rtl8169_private *tp,
int mac_version;
} mac_info[] = {
/* 8168F family. */
+ { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
{ 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
{ 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
{ 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
/* 8101 family. */
+ { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
{ 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
{ 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
{ 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
rtl_writephy(tp, 0x1f, 0x0000);
}
+static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
+{
+ /* For 4-corner performance improve */
+ rtl_writephy(tp, 0x1f, 0x0005);
+ rtl_writephy(tp, 0x05, 0x8b80);
+ rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
+ rtl_writephy(tp, 0x1f, 0x0000);
+
+ /* PHY auto speed down */
+ rtl_writephy(tp, 0x1f, 0x0007);
+ rtl_writephy(tp, 0x1e, 0x002d);
+ rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
+ rtl_writephy(tp, 0x1f, 0x0000);
+ rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
+
+ /* Improve 10M EEE waveform */
+ rtl_writephy(tp, 0x1f, 0x0005);
+ rtl_writephy(tp, 0x05, 0x8b86);
+ rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
+ rtl_writephy(tp, 0x1f, 0x0000);
+}
+
static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
{
static const struct phy_reg phy_reg_init[] = {
rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
- /* For 4-corner performance improve */
- rtl_writephy(tp, 0x1f, 0x0005);
- rtl_writephy(tp, 0x05, 0x8b80);
- rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
- rtl_writephy(tp, 0x1f, 0x0000);
-
- /* PHY auto speed down */
- rtl_writephy(tp, 0x1f, 0x0007);
- rtl_writephy(tp, 0x1e, 0x002d);
- rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
- rtl_writephy(tp, 0x1f, 0x0000);
- rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
-
- /* Improve 10M EEE waveform */
- rtl_writephy(tp, 0x1f, 0x0005);
- rtl_writephy(tp, 0x05, 0x8b86);
- rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
- rtl_writephy(tp, 0x1f, 0x0000);
+ rtl8168f_hw_phy_config(tp);
/* Improve 2-pair detection performance */
rtl_writephy(tp, 0x1f, 0x0005);
{
rtl_apply_firmware(tp);
- /* For 4-corner performance improve */
+ rtl8168f_hw_phy_config(tp);
+}
+
+static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
+{
+ void __iomem *ioaddr = tp->mmio_addr;
+ static const struct phy_reg phy_reg_init[] = {
+ /* Channel estimation fine tune */
+ { 0x1f, 0x0003 },
+ { 0x09, 0xa20f },
+ { 0x1f, 0x0000 },
+
+ /* Modify green table for giga & fnet */
+ { 0x1f, 0x0005 },
+ { 0x05, 0x8b55 },
+ { 0x06, 0x0000 },
+ { 0x05, 0x8b5e },
+ { 0x06, 0x0000 },
+ { 0x05, 0x8b67 },
+ { 0x06, 0x0000 },
+ { 0x05, 0x8b70 },
+ { 0x06, 0x0000 },
+ { 0x1f, 0x0000 },
+ { 0x1f, 0x0007 },
+ { 0x1e, 0x0078 },
+ { 0x17, 0x0000 },
+ { 0x19, 0x00aa },
+ { 0x1f, 0x0000 },
+
+ /* Modify green table for 10M */
+ { 0x1f, 0x0005 },
+ { 0x05, 0x8b79 },
+ { 0x06, 0xaa00 },
+ { 0x1f, 0x0000 },
+
+ /* Disable hiimpedance detection (RTCT) */
+ { 0x1f, 0x0003 },
+ { 0x01, 0x328a },
+ { 0x1f, 0x0000 }
+ };
+
+
+ rtl_apply_firmware(tp);
+
+ rtl8168f_hw_phy_config(tp);
+
+ /* Improve 2-pair detection performance */
rtl_writephy(tp, 0x1f, 0x0005);
- rtl_writephy(tp, 0x05, 0x8b80);
- rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
+ rtl_writephy(tp, 0x05, 0x8b85);
+ rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
rtl_writephy(tp, 0x1f, 0x0000);
- /* PHY auto speed down */
- rtl_writephy(tp, 0x1f, 0x0007);
- rtl_writephy(tp, 0x1e, 0x002d);
- rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
+ rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+
+ /* Modify green table for giga */
+ rtl_writephy(tp, 0x1f, 0x0005);
+ rtl_writephy(tp, 0x05, 0x8b54);
+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
+ rtl_writephy(tp, 0x05, 0x8b5d);
+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
+ rtl_writephy(tp, 0x05, 0x8a7c);
+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
+ rtl_writephy(tp, 0x05, 0x8a7f);
+ rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
+ rtl_writephy(tp, 0x05, 0x8a82);
+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
+ rtl_writephy(tp, 0x05, 0x8a85);
+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
+ rtl_writephy(tp, 0x05, 0x8a88);
+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
rtl_writephy(tp, 0x1f, 0x0000);
- rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
- /* Improve 10M EEE waveform */
+ /* uc same-seed solution */
rtl_writephy(tp, 0x1f, 0x0005);
- rtl_writephy(tp, 0x05, 0x8b86);
- rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
+ rtl_writephy(tp, 0x05, 0x8b85);
+ rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
+ rtl_writephy(tp, 0x1f, 0x0000);
+
+ /* eee setting */
+ rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
+ rtl_writephy(tp, 0x1f, 0x0005);
+ rtl_writephy(tp, 0x05, 0x8b85);
+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
+ rtl_writephy(tp, 0x1f, 0x0004);
+ rtl_writephy(tp, 0x1f, 0x0007);
+ rtl_writephy(tp, 0x1e, 0x0020);
+ rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
+ rtl_writephy(tp, 0x1f, 0x0000);
+ rtl_writephy(tp, 0x0d, 0x0007);
+ rtl_writephy(tp, 0x0e, 0x003c);
+ rtl_writephy(tp, 0x0d, 0x4007);
+ rtl_writephy(tp, 0x0e, 0x0000);
+ rtl_writephy(tp, 0x0d, 0x0000);
+
+ /* Green feature */
+ rtl_writephy(tp, 0x1f, 0x0003);
+ rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
+ rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
rtl_writephy(tp, 0x1f, 0x0000);
}
rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}
+static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
+{
+ void __iomem *ioaddr = tp->mmio_addr;
+
+ /* Disable ALDPS before setting firmware */
+ rtl_writephy(tp, 0x1f, 0x0000);
+ rtl_writephy(tp, 0x18, 0x0310);
+ msleep(20);
+
+ rtl_apply_firmware(tp);
+
+ /* EEE setting */
+ rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+ rtl_writephy(tp, 0x1f, 0x0004);
+ rtl_writephy(tp, 0x10, 0x401f);
+ rtl_writephy(tp, 0x19, 0x7030);
+ rtl_writephy(tp, 0x1f, 0x0000);
+}
+
static void rtl_hw_phy_config(struct net_device *dev)
{
struct rtl8169_private *tp = netdev_priv(dev);
rtl8168f_2_hw_phy_config(tp);
break;
+ case RTL_GIGA_MAC_VER_37:
+ rtl8402_hw_phy_config(tp);
+ break;
+
+ case RTL_GIGA_MAC_VER_38:
+ rtl8411_hw_phy_config(tp);
+ break;
+
default:
break;
}
case RTL_GIGA_MAC_VER_32:
case RTL_GIGA_MAC_VER_33:
case RTL_GIGA_MAC_VER_34:
+ case RTL_GIGA_MAC_VER_37:
+ case RTL_GIGA_MAC_VER_38:
RTL_W32(RxConfig, RTL_R32(RxConfig) |
AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
break;
static void r810x_pll_power_down(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+
if (rtl_wol_pll_power_down(tp))
return;
r810x_phy_power_down(tp);
+
+ switch (tp->mac_version) {
+ case RTL_GIGA_MAC_VER_07:
+ case RTL_GIGA_MAC_VER_08:
+ case RTL_GIGA_MAC_VER_09:
+ case RTL_GIGA_MAC_VER_10:
+ case RTL_GIGA_MAC_VER_13:
+ case RTL_GIGA_MAC_VER_16:
+ break;
+ default:
+ RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
+ break;
+ }
}
static void r810x_pll_power_up(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+
r810x_phy_power_up(tp);
+
+ switch (tp->mac_version) {
+ case RTL_GIGA_MAC_VER_07:
+ case RTL_GIGA_MAC_VER_08:
+ case RTL_GIGA_MAC_VER_09:
+ case RTL_GIGA_MAC_VER_10:
+ case RTL_GIGA_MAC_VER_13:
+ case RTL_GIGA_MAC_VER_16:
+ break;
+ default:
+ RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
+ break;
+ }
}
static void r8168_phy_power_up(struct rtl8169_private *tp)
{
void __iomem *ioaddr = tp->mmio_addr;
- if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
- tp->mac_version == RTL_GIGA_MAC_VER_28 ||
- tp->mac_version == RTL_GIGA_MAC_VER_31) &&
- r8168dp_check_dash(tp)) {
- return;
- }
-
switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_25:
case RTL_GIGA_MAC_VER_26:
case RTL_GIGA_MAC_VER_16:
case RTL_GIGA_MAC_VER_29:
case RTL_GIGA_MAC_VER_30:
+ case RTL_GIGA_MAC_VER_37:
ops->down = r810x_pll_power_down;
ops->up = r810x_pll_power_up;
break;
case RTL_GIGA_MAC_VER_34:
case RTL_GIGA_MAC_VER_35:
case RTL_GIGA_MAC_VER_36:
+ case RTL_GIGA_MAC_VER_38:
ops->down = r8168_pll_power_down;
ops->up = r8168_pll_power_up;
break;
udelay(20);
} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
tp->mac_version == RTL_GIGA_MAC_VER_35 ||
- tp->mac_version == RTL_GIGA_MAC_VER_36) {
+ tp->mac_version == RTL_GIGA_MAC_VER_36 ||
+ tp->mac_version == RTL_GIGA_MAC_VER_37 ||
+ tp->mac_version == RTL_GIGA_MAC_VER_38) {
RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
udelay(100);
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
}
-static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
+static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
+{
+ if (tp->csi_ops.write)
+ tp->csi_ops.write(tp->mmio_addr, addr, value);
+}
+
+static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
+{
+ if (tp->csi_ops.read)
+ return tp->csi_ops.read(tp->mmio_addr, addr);
+ else
+ return ~0;
+}
+
+static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
{
u32 csi;
- csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
- rtl_csi_write(ioaddr, 0x070c, csi | bits);
+ csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
+ rtl_csi_write(tp, 0x070c, csi | bits);
+}
+
+static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
+{
+ rtl_csi_access_enable(tp, 0x17000000);
+}
+
+static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
+{
+ rtl_csi_access_enable(tp, 0x27000000);
+}
+
+static void r8169_csi_write(void __iomem *ioaddr, int addr, int value)
+{
+ unsigned int i;
+
+ RTL_W32(CSIDR, value);
+ RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
+ CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
+
+ for (i = 0; i < 100; i++) {
+ if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
+ break;
+ udelay(10);
+ }
+}
+
+static u32 r8169_csi_read(void __iomem *ioaddr, int addr)
+{
+ u32 value = ~0x00;
+ unsigned int i;
+
+ RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
+ CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
+
+ for (i = 0; i < 100; i++) {
+ if (RTL_R32(CSIAR) & CSIAR_FLAG) {
+ value = RTL_R32(CSIDR);
+ break;
+ }
+ udelay(10);
+ }
+
+ return value;
+}
+
+static void r8402_csi_write(void __iomem *ioaddr, int addr, int value)
+{
+ unsigned int i;
+
+ RTL_W32(CSIDR, value);
+ RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
+ CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
+ CSIAR_FUNC_NIC);
+
+ for (i = 0; i < 100; i++) {
+ if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
+ break;
+ udelay(10);
+ }
}
-static void rtl_csi_access_enable_1(void __iomem *ioaddr)
+static u32 r8402_csi_read(void __iomem *ioaddr, int addr)
{
- rtl_csi_access_enable(ioaddr, 0x17000000);
+ u32 value = ~0x00;
+ unsigned int i;
+
+ RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
+ CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
+
+ for (i = 0; i < 100; i++) {
+ if (RTL_R32(CSIAR) & CSIAR_FLAG) {
+ value = RTL_R32(CSIDR);
+ break;
+ }
+ udelay(10);
+ }
+
+ return value;
}
-static void rtl_csi_access_enable_2(void __iomem *ioaddr)
+static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
{
- rtl_csi_access_enable(ioaddr, 0x27000000);
+ struct csi_ops *ops = &tp->csi_ops;
+
+ switch (tp->mac_version) {
+ case RTL_GIGA_MAC_VER_01:
+ case RTL_GIGA_MAC_VER_02:
+ case RTL_GIGA_MAC_VER_03:
+ case RTL_GIGA_MAC_VER_04:
+ case RTL_GIGA_MAC_VER_05:
+ case RTL_GIGA_MAC_VER_06:
+ case RTL_GIGA_MAC_VER_10:
+ case RTL_GIGA_MAC_VER_11:
+ case RTL_GIGA_MAC_VER_12:
+ case RTL_GIGA_MAC_VER_13:
+ case RTL_GIGA_MAC_VER_14:
+ case RTL_GIGA_MAC_VER_15:
+ case RTL_GIGA_MAC_VER_16:
+ case RTL_GIGA_MAC_VER_17:
+ ops->write = NULL;
+ ops->read = NULL;
+ break;
+
+ case RTL_GIGA_MAC_VER_37:
+ case RTL_GIGA_MAC_VER_38:
+ ops->write = r8402_csi_write;
+ ops->read = r8402_csi_read;
+ break;
+
+ default:
+ ops->write = r8169_csi_write;
+ ops->read = r8169_csi_read;
+ break;
+ }
}
struct ephy_info {
PktCntrDisable | \
Mac_dbgo_sel)
-static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
+
RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
}
-static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
{
- rtl_hw_start_8168bb(ioaddr, pdev);
+ void __iomem *ioaddr = tp->mmio_addr;
+
+ rtl_hw_start_8168bb(tp);
RTL_W8(MaxTxPacketSize, TxPacketMax);
RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
}
-static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
+static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
+
RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}
-static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
static const struct ephy_info e_info_8168cp[] = {
{ 0x01, 0, 0x0001 },
{ 0x02, 0x0800, 0x1000 },
{ 0x07, 0, 0x2000 }
};
- rtl_csi_access_enable_2(ioaddr);
+ rtl_csi_access_enable_2(tp);
rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
- __rtl_hw_start_8168cp(ioaddr, pdev);
+ __rtl_hw_start_8168cp(tp);
}
-static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
{
- rtl_csi_access_enable_2(ioaddr);
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
+
+ rtl_csi_access_enable_2(tp);
RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}
-static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
{
- rtl_csi_access_enable_2(ioaddr);
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
+
+ rtl_csi_access_enable_2(tp);
RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}
-static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
static const struct ephy_info e_info_8168c_1[] = {
{ 0x02, 0x0800, 0x1000 },
{ 0x03, 0, 0x0002 },
{ 0x06, 0x0080, 0x0000 }
};
- rtl_csi_access_enable_2(ioaddr);
+ rtl_csi_access_enable_2(tp);
RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
- __rtl_hw_start_8168cp(ioaddr, pdev);
+ __rtl_hw_start_8168cp(tp);
}
-static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
static const struct ephy_info e_info_8168c_2[] = {
{ 0x01, 0, 0x0001 },
{ 0x03, 0x0400, 0x0220 }
};
- rtl_csi_access_enable_2(ioaddr);
+ rtl_csi_access_enable_2(tp);
rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
- __rtl_hw_start_8168cp(ioaddr, pdev);
+ __rtl_hw_start_8168cp(tp);
}
-static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
{
- rtl_hw_start_8168c_2(ioaddr, pdev);
+ rtl_hw_start_8168c_2(tp);
}
-static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
{
- rtl_csi_access_enable_2(ioaddr);
+ rtl_csi_access_enable_2(tp);
- __rtl_hw_start_8168cp(ioaddr, pdev);
+ __rtl_hw_start_8168cp(tp);
}
-static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168d(struct rtl8169_private *tp)
{
- rtl_csi_access_enable_2(ioaddr);
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
+
+ rtl_csi_access_enable_2(tp);
rtl_disable_clock_request(pdev);
RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}
-static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
{
- rtl_csi_access_enable_1(ioaddr);
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
+
+ rtl_csi_access_enable_1(tp);
rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
rtl_disable_clock_request(pdev);
}
-static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
static const struct ephy_info e_info_8168d_4[] = {
{ 0x0b, ~0, 0x48 },
{ 0x19, 0x20, 0x50 },
};
int i;
- rtl_csi_access_enable_1(ioaddr);
+ rtl_csi_access_enable_1(tp);
rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
rtl_enable_clock_request(pdev);
}
-static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
static const struct ephy_info e_info_8168e_1[] = {
{ 0x00, 0x0200, 0x0100 },
{ 0x00, 0x0000, 0x0004 },
{ 0x0a, 0x0000, 0x0040 }
};
- rtl_csi_access_enable_2(ioaddr);
+ rtl_csi_access_enable_2(tp);
rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
}
-static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
static const struct ephy_info e_info_8168e_2[] = {
{ 0x09, 0x0000, 0x0080 },
{ 0x19, 0x0000, 0x0224 }
};
- rtl_csi_access_enable_1(ioaddr);
+ rtl_csi_access_enable_1(tp);
rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
}
-static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8168f(struct rtl8169_private *tp)
{
- static const struct ephy_info e_info_8168f_1[] = {
- { 0x06, 0x00c0, 0x0020 },
- { 0x08, 0x0001, 0x0002 },
- { 0x09, 0x0000, 0x0080 },
- { 0x19, 0x0000, 0x0224 }
- };
-
- rtl_csi_access_enable_1(ioaddr);
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
- rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
+ rtl_csi_access_enable_2(tp);
rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
- rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
- ERIAR_EXGMAC);
RTL_W8(MaxTxPacketSize, EarlySize);
RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
+ RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
+ RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
+ RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
+}
+
+static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
+{
+ void __iomem *ioaddr = tp->mmio_addr;
+ static const struct ephy_info e_info_8168f_1[] = {
+ { 0x06, 0x00c0, 0x0020 },
+ { 0x08, 0x0001, 0x0002 },
+ { 0x09, 0x0000, 0x0080 },
+ { 0x19, 0x0000, 0x0224 }
+ };
+
+ rtl_hw_start_8168f(tp);
+
+ rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
+
+ rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
+ ERIAR_EXGMAC);
/* Adjust EEE LED frequency */
RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
+}
- RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
- RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
- RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
+static void rtl_hw_start_8411(struct rtl8169_private *tp)
+{
+ void __iomem *ioaddr = tp->mmio_addr;
+ static const struct ephy_info e_info_8168f_1[] = {
+ { 0x06, 0x00c0, 0x0020 },
+ { 0x0f, 0xffff, 0x5200 },
+ { 0x1e, 0x0000, 0x4000 },
+ { 0x19, 0x0000, 0x0224 }
+ };
+
+ rtl_hw_start_8168f(tp);
+
+ rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
+
+ rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000,
+ ERIAR_EXGMAC);
}
static void rtl_hw_start_8168(struct net_device *dev)
{
struct rtl8169_private *tp = netdev_priv(dev);
void __iomem *ioaddr = tp->mmio_addr;
- struct pci_dev *pdev = tp->pci_dev;
RTL_W8(Cfg9346, Cfg9346_Unlock);
switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_11:
- rtl_hw_start_8168bb(ioaddr, pdev);
+ rtl_hw_start_8168bb(tp);
break;
case RTL_GIGA_MAC_VER_12:
case RTL_GIGA_MAC_VER_17:
- rtl_hw_start_8168bef(ioaddr, pdev);
+ rtl_hw_start_8168bef(tp);
break;
case RTL_GIGA_MAC_VER_18:
- rtl_hw_start_8168cp_1(ioaddr, pdev);
+ rtl_hw_start_8168cp_1(tp);
break;
case RTL_GIGA_MAC_VER_19:
- rtl_hw_start_8168c_1(ioaddr, pdev);
+ rtl_hw_start_8168c_1(tp);
break;
case RTL_GIGA_MAC_VER_20:
- rtl_hw_start_8168c_2(ioaddr, pdev);
+ rtl_hw_start_8168c_2(tp);
break;
case RTL_GIGA_MAC_VER_21:
- rtl_hw_start_8168c_3(ioaddr, pdev);
+ rtl_hw_start_8168c_3(tp);
break;
case RTL_GIGA_MAC_VER_22:
- rtl_hw_start_8168c_4(ioaddr, pdev);
+ rtl_hw_start_8168c_4(tp);
break;
case RTL_GIGA_MAC_VER_23:
- rtl_hw_start_8168cp_2(ioaddr, pdev);
+ rtl_hw_start_8168cp_2(tp);
break;
case RTL_GIGA_MAC_VER_24:
- rtl_hw_start_8168cp_3(ioaddr, pdev);
+ rtl_hw_start_8168cp_3(tp);
break;
case RTL_GIGA_MAC_VER_25:
case RTL_GIGA_MAC_VER_26:
case RTL_GIGA_MAC_VER_27:
- rtl_hw_start_8168d(ioaddr, pdev);
+ rtl_hw_start_8168d(tp);
break;
case RTL_GIGA_MAC_VER_28:
- rtl_hw_start_8168d_4(ioaddr, pdev);
+ rtl_hw_start_8168d_4(tp);
break;
case RTL_GIGA_MAC_VER_31:
- rtl_hw_start_8168dp(ioaddr, pdev);
+ rtl_hw_start_8168dp(tp);
break;
case RTL_GIGA_MAC_VER_32:
case RTL_GIGA_MAC_VER_33:
- rtl_hw_start_8168e_1(ioaddr, pdev);
+ rtl_hw_start_8168e_1(tp);
break;
case RTL_GIGA_MAC_VER_34:
- rtl_hw_start_8168e_2(ioaddr, pdev);
+ rtl_hw_start_8168e_2(tp);
break;
case RTL_GIGA_MAC_VER_35:
case RTL_GIGA_MAC_VER_36:
- rtl_hw_start_8168f_1(ioaddr, pdev);
+ rtl_hw_start_8168f_1(tp);
+ break;
+
+ case RTL_GIGA_MAC_VER_38:
+ rtl_hw_start_8411(tp);
break;
default:
PktCntrDisable | \
Mac_dbgo_sel)
-static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
static const struct ephy_info e_info_8102e_1[] = {
{ 0x01, 0, 0x6e65 },
{ 0x02, 0, 0x091f },
};
u8 cfg1;
- rtl_csi_access_enable_2(ioaddr);
+ rtl_csi_access_enable_2(tp);
RTL_W8(DBG_REG, FIX_NAK_1);
rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
}
-static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
{
- rtl_csi_access_enable_2(ioaddr);
+ void __iomem *ioaddr = tp->mmio_addr;
+ struct pci_dev *pdev = tp->pci_dev;
+
+ rtl_csi_access_enable_2(tp);
rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
}
-static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
{
- rtl_hw_start_8102e_2(ioaddr, pdev);
+ rtl_hw_start_8102e_2(tp);
- rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
+ rtl_ephy_write(tp->mmio_addr, 0x03, 0xc2f9);
}
-static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
{
+ void __iomem *ioaddr = tp->mmio_addr;
static const struct ephy_info e_info_8105e_1[] = {
{ 0x07, 0, 0x4000 },
{ 0x19, 0, 0x0200 },
rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
}
-static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
+static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
{
- rtl_hw_start_8105e_1(ioaddr, pdev);
+ void __iomem *ioaddr = tp->mmio_addr;
+
+ rtl_hw_start_8105e_1(tp);
rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
}
+static void rtl_hw_start_8402(struct rtl8169_private *tp)
+{
+ void __iomem *ioaddr = tp->mmio_addr;
+ static const struct ephy_info e_info_8402[] = {
+ { 0x19, 0xffff, 0xff64 },
+ { 0x1e, 0, 0x4000 }
+ };
+
+ rtl_csi_access_enable_2(tp);
+
+ /* Force LAN exit from ASPM if Rx/Tx are not idle */
+ RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
+
+ RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
+ RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
+
+ rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402));
+
+ rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
+
+ rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
+ rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
+ rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
+ rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
+ rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+ rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+ rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00,
+ ERIAR_EXGMAC);
+}
+
static void rtl_hw_start_8101(struct net_device *dev)
{
struct rtl8169_private *tp = netdev_priv(dev);
switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_07:
- rtl_hw_start_8102e_1(ioaddr, pdev);
+ rtl_hw_start_8102e_1(tp);
break;
case RTL_GIGA_MAC_VER_08:
- rtl_hw_start_8102e_3(ioaddr, pdev);
+ rtl_hw_start_8102e_3(tp);
break;
case RTL_GIGA_MAC_VER_09:
- rtl_hw_start_8102e_2(ioaddr, pdev);
+ rtl_hw_start_8102e_2(tp);
break;
case RTL_GIGA_MAC_VER_29:
- rtl_hw_start_8105e_1(ioaddr, pdev);
+ rtl_hw_start_8105e_1(tp);
break;
case RTL_GIGA_MAC_VER_30:
- rtl_hw_start_8105e_2(ioaddr, pdev);
+ rtl_hw_start_8105e_2(tp);
+ break;
+
+ case RTL_GIGA_MAC_VER_37:
+ rtl_hw_start_8402(tp);
break;
}
u32 opts[2];
int frags;
- if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
+ if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
goto err_stop_0;
}
mmiowb();
- if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
+ if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
/* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
* not miss a ring update when it notices a stopped queue.
*/
* can't.
*/
smp_mb();
- if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
+ if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
netif_wake_queue(dev);
}
*/
smp_mb();
if (netif_queue_stopped(dev) &&
- (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
+ TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
netif_wake_queue(dev);
}
/*
pm_runtime_get_sync(&pdev->dev);
/*
- * Rx and Tx desscriptors needs 256 bytes alignment.
+ * Rx and Tx descriptors needs 256 bytes alignment.
* dma_alloc_coherent provides more.
*/
tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
rtl_init_mdio_ops(tp);
rtl_init_pll_power_ops(tp);
rtl_init_jumbo_ops(tp);
+ rtl_init_csi_ops(tp);
rtl8169_print_mac_version(tp);
/*
* Ethernet driver for S6105 on chip network device
* (c)2008 emlix GmbH http://www.emlix.com
- * Authors: Oskar Schirmer <os@emlix.com>
+ * Authors: Oskar Schirmer <oskar@scara.com>
* Daniel Gloeckner <dg@emlix.com>
*
* This program is free software; you can redistribute it and/or
do {
unsigned long flags;
spin_lock_irqsave(&pd->lock, flags);
- for (i = 0; i < sizeof(pd->stats) / sizeof(unsigned long); i++)
+ for (i = 0; i < ARRAY_SIZE(pd->stats); i++)
pd->stats[i] =
pd->carry[i] << (S6_GMAC_STAT_SIZE_MIN - 1);
s6gmac_stats_collect(pd, &statinf[0][0]);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("S6105 on chip Ethernet driver");
- MODULE_AUTHOR("Oskar Schirmer <os@emlix.com>");
+ MODULE_AUTHOR("Oskar Schirmer <oskar@scara.com>");
out:
if (master)
WRITE_REG(priv, regINIT_SEMAPHORE, 1);
- if (fw)
- release_firmware(fw);
+
+ release_firmware(fw);
if (rc) {
netdev_err(priv->ndev, "firmware loading failed\n");
static void print_rxfd(struct rxf_desc *rxfd)
{
- DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
+ DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
"info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
}
/* these fields are used for info purposes only
* so we can have them same for all ports of the board */
ndev->if_port = port;
- ndev->base_addr = pciaddr;
- ndev->mem_start = pciaddr;
- ndev->mem_end = pciaddr + regionSize;
- ndev->irq = pdev->irq;
ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
| NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
NETIF_F_HW_VLAN_FILTER | NETIF_F_RXCSUM
kingsun-sir.
config EP7211_DONGLE
- tristate "EP7211 I/R support"
- depends on IRTTY_SIR && ARCH_EP7211 && IRDA && EXPERIMENTAL
+ tristate "Cirrus Logic clps711x I/R support"
+ depends on IRTTY_SIR && ARCH_CLPS711X && IRDA && EXPERIMENTAL
help
Say Y here if you want to build support for the Cirrus logic
EP7211 chipset's infrared module.
tristate "Alchemy IrDA SIR/FIR"
depends on IRDA && MIPS_ALCHEMY
help
- Say Y/M here to build suppor the the IrDA peripheral on the
+ Say Y/M here to build support the IrDA peripheral on the
Alchemy Au1000 and Au1100 SoCs.
Say M to build a module; it will be called au1k_ir.ko
config SMC_IRCC_FIR
- tristate "SMSC IrCC (EXPERIMENTAL)"
- depends on EXPERIMENTAL && IRDA && ISA_DMA_API
+ tristate "SMSC IrCC"
+ depends on IRDA && ISA_DMA_API
help
Say Y here if you want to build support for the SMC Infrared
Communications Controller. It is used in a wide variety of
using the SO_TIMESTAMPING API.
In order for this to work, your MAC driver must also
- implement the skb_tx_timetamp() function.
+ implement the skb_tx_timestamp() function.
config PTP_1588_CLOCK_PCH
tristate "Intel PCH EG20T as PTP clock"
depends on PCH_GBE
help
This driver adds support for using the PCH EG20T as a PTP
- clock. This clock is only useful if your PTP programs are
- getting hardware time stamps on the PTP Ethernet packets
- using the SO_TIMESTAMPING API.
+ clock. The hardware supports time stamping of PTP packets
+ when using the end-to-end delay (E2E) mechansim. The peer
+ delay mechansim (P2P) is not supported.
+
+ This clock is only useful if your PTP programs are getting
+ hardware time stamps on the PTP Ethernet packets using the
+ SO_TIMESTAMPING API.
To compile this driver as a module, choose M here: the module
will be called ptp_pch.
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
-#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/mfd/tps65910.h>
+#include <linux/regulator/of_regulator.h>
#define TPS65910_SUPPLY_STATE_ENABLED 0x1
#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
- /* supported VIO voltages in milivolts */
+ /* supported VIO voltages in millivolts */
static const u16 VIO_VSEL_table[] = {
1500, 1800, 2500, 3300,
};
/* VSEL tables for TPS65910 specific LDOs and dcdc's */
- /* supported VDD3 voltages in milivolts */
+ /* supported VDD3 voltages in millivolts */
static const u16 VDD3_VSEL_table[] = {
5000,
};
- /* supported VDIG1 voltages in milivolts */
+ /* supported VDIG1 voltages in millivolts */
static const u16 VDIG1_VSEL_table[] = {
1200, 1500, 1800, 2700,
};
- /* supported VDIG2 voltages in milivolts */
+ /* supported VDIG2 voltages in millivolts */
static const u16 VDIG2_VSEL_table[] = {
1000, 1100, 1200, 1800,
};
- /* supported VPLL voltages in milivolts */
+ /* supported VPLL voltages in millivolts */
static const u16 VPLL_VSEL_table[] = {
1000, 1100, 1800, 2500,
};
- /* supported VDAC voltages in milivolts */
+ /* supported VDAC voltages in millivolts */
static const u16 VDAC_VSEL_table[] = {
1800, 2600, 2800, 2850,
};
- /* supported VAUX1 voltages in milivolts */
+ /* supported VAUX1 voltages in millivolts */
static const u16 VAUX1_VSEL_table[] = {
1800, 2500, 2800, 2850,
};
- /* supported VAUX2 voltages in milivolts */
+ /* supported VAUX2 voltages in millivolts */
static const u16 VAUX2_VSEL_table[] = {
1800, 2800, 2900, 3300,
};
- /* supported VAUX33 voltages in milivolts */
+ /* supported VAUX33 voltages in millivolts */
static const u16 VAUX33_VSEL_table[] = {
1800, 2000, 2800, 3300,
};
- /* supported VMMC voltages in milivolts */
+ /* supported VMMC voltages in millivolts */
static const u16 VMMC_VSEL_table[] = {
1800, 2800, 3000, 3300,
};
static struct tps_info tps65910_regs[] = {
{
- .name = "VRTC",
+ .name = "vrtc",
.enable_time_us = 2200,
},
{
- .name = "VIO",
+ .name = "vio",
.min_uV = 1500000,
.max_uV = 3300000,
.n_voltages = ARRAY_SIZE(VIO_VSEL_table),
.enable_time_us = 350,
},
{
- .name = "VDD1",
+ .name = "vdd1",
.min_uV = 600000,
.max_uV = 4500000,
.enable_time_us = 350,
},
{
- .name = "VDD2",
+ .name = "vdd2",
.min_uV = 600000,
.max_uV = 4500000,
.enable_time_us = 350,
},
{
- .name = "VDD3",
+ .name = "vdd3",
.min_uV = 5000000,
.max_uV = 5000000,
.n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
.enable_time_us = 200,
},
{
- .name = "VDIG1",
+ .name = "vdig1",
.min_uV = 1200000,
.max_uV = 2700000,
.n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
.enable_time_us = 100,
},
{
- .name = "VDIG2",
+ .name = "vdig2",
.min_uV = 1000000,
.max_uV = 1800000,
.n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
.enable_time_us = 100,
},
{
- .name = "VPLL",
+ .name = "vpll",
.min_uV = 1000000,
.max_uV = 2500000,
.n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
.enable_time_us = 100,
},
{
- .name = "VDAC",
+ .name = "vdac",
.min_uV = 1800000,
.max_uV = 2850000,
.n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
.enable_time_us = 100,
},
{
- .name = "VAUX1",
+ .name = "vaux1",
.min_uV = 1800000,
.max_uV = 2850000,
.n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
.enable_time_us = 100,
},
{
- .name = "VAUX2",
+ .name = "vaux2",
.min_uV = 1800000,
.max_uV = 3300000,
.n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
.enable_time_us = 100,
},
{
- .name = "VAUX33",
+ .name = "vaux33",
.min_uV = 1800000,
.max_uV = 3300000,
.n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
.enable_time_us = 100,
},
{
- .name = "VMMC",
+ .name = "vmmc",
.min_uV = 1800000,
.max_uV = 3300000,
.n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
static struct tps_info tps65911_regs[] = {
{
- .name = "VRTC",
+ .name = "vrtc",
.enable_time_us = 2200,
},
{
- .name = "VIO",
+ .name = "vio",
.min_uV = 1500000,
.max_uV = 3300000,
.n_voltages = ARRAY_SIZE(VIO_VSEL_table),
.enable_time_us = 350,
},
{
- .name = "VDD1",
+ .name = "vdd1",
.min_uV = 600000,
.max_uV = 4500000,
.n_voltages = 73,
.enable_time_us = 350,
},
{
- .name = "VDD2",
+ .name = "vdd2",
.min_uV = 600000,
.max_uV = 4500000,
.n_voltages = 73,
.enable_time_us = 350,
},
{
- .name = "VDDCTRL",
+ .name = "vddctrl",
.min_uV = 600000,
.max_uV = 1400000,
.n_voltages = 65,
.enable_time_us = 900,
},
{
- .name = "LDO1",
+ .name = "ldo1",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 47,
.enable_time_us = 420,
},
{
- .name = "LDO2",
+ .name = "ldo2",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 47,
.enable_time_us = 420,
},
{
- .name = "LDO3",
+ .name = "ldo3",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 24,
.enable_time_us = 230,
},
{
- .name = "LDO4",
+ .name = "ldo4",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 47,
.enable_time_us = 230,
},
{
- .name = "LDO5",
+ .name = "ldo5",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 24,
.enable_time_us = 230,
},
{
- .name = "LDO6",
+ .name = "ldo6",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 24,
.enable_time_us = 230,
},
{
- .name = "LDO7",
+ .name = "ldo7",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 24,
.enable_time_us = 230,
},
{
- .name = "LDO8",
+ .name = "ldo8",
.min_uV = 1000000,
.max_uV = 3300000,
.n_voltages = 24,
}
}
-static int tps65910_is_enabled(struct regulator_dev *dev)
-{
- struct tps65910_reg *pmic = rdev_get_drvdata(dev);
- int reg, value, id = rdev_get_id(dev);
-
- reg = pmic->get_ctrl_reg(id);
- if (reg < 0)
- return reg;
-
- value = tps65910_reg_read(pmic, reg);
- if (value < 0)
- return value;
-
- return value & TPS65910_SUPPLY_STATE_ENABLED;
-}
-
-static int tps65910_enable(struct regulator_dev *dev)
-{
- struct tps65910_reg *pmic = rdev_get_drvdata(dev);
- struct tps65910 *mfd = pmic->mfd;
- int reg, id = rdev_get_id(dev);
-
- reg = pmic->get_ctrl_reg(id);
- if (reg < 0)
- return reg;
-
- return tps65910_set_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
-}
-
-static int tps65910_disable(struct regulator_dev *dev)
-{
- struct tps65910_reg *pmic = rdev_get_drvdata(dev);
- struct tps65910 *mfd = pmic->mfd;
- int reg, id = rdev_get_id(dev);
-
- reg = pmic->get_ctrl_reg(id);
- if (reg < 0)
- return reg;
-
- return tps65910_clear_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
-}
-
static int tps65910_enable_time(struct regulator_dev *dev)
{
struct tps65910_reg *pmic = rdev_get_drvdata(dev);
return -EINVAL;
}
-static int tps65910_get_voltage(struct regulator_dev *dev)
+static int tps65910_get_voltage_sel(struct regulator_dev *dev)
{
struct tps65910_reg *pmic = rdev_get_drvdata(dev);
- int reg, value, id = rdev_get_id(dev), voltage = 0;
+ int reg, value, id = rdev_get_id(dev);
reg = pmic->get_ctrl_reg(id);
if (reg < 0)
return -EINVAL;
}
- voltage = pmic->info[id]->voltage_table[value] * 1000;
-
- return voltage;
+ return value;
}
static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
return 5 * 1000 * 1000;
}
-static int tps65911_get_voltage(struct regulator_dev *dev)
+static int tps65911_get_voltage_sel(struct regulator_dev *dev)
{
struct tps65910_reg *pmic = rdev_get_drvdata(dev);
- int step_mv, id = rdev_get_id(dev);
+ int id = rdev_get_id(dev);
u8 value, reg;
reg = pmic->get_ctrl_reg(id);
case TPS65911_REG_LDO4:
value &= LDO1_SEL_MASK;
value >>= LDO_SEL_SHIFT;
- /* The first 5 values of the selector correspond to 1V */
- if (value < 5)
- value = 0;
- else
- value -= 4;
-
- step_mv = 50;
break;
case TPS65911_REG_LDO3:
case TPS65911_REG_LDO5:
case TPS65911_REG_LDO8:
value &= LDO3_SEL_MASK;
value >>= LDO_SEL_SHIFT;
- /* The first 3 values of the selector correspond to 1V */
- if (value < 3)
- value = 0;
- else
- value -= 2;
-
- step_mv = 100;
break;
case TPS65910_REG_VIO:
value &= LDO_SEL_MASK;
value >>= LDO_SEL_SHIFT;
- return pmic->info[id]->voltage_table[value] * 1000;
+ break;
default:
return -EINVAL;
}
- return (LDO_MIN_VOLT + value * step_mv) * 1000;
+ return value;
}
static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
/* Regulator ops (except VRTC) */
static struct regulator_ops tps65910_ops_dcdc = {
- .is_enabled = tps65910_is_enabled,
- .enable = tps65910_enable,
- .disable = tps65910_disable,
+ .is_enabled = regulator_is_enabled_regmap,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
.enable_time = tps65910_enable_time,
.set_mode = tps65910_set_mode,
.get_mode = tps65910_get_mode,
};
static struct regulator_ops tps65910_ops_vdd3 = {
- .is_enabled = tps65910_is_enabled,
- .enable = tps65910_enable,
- .disable = tps65910_disable,
+ .is_enabled = regulator_is_enabled_regmap,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
.enable_time = tps65910_enable_time,
.set_mode = tps65910_set_mode,
.get_mode = tps65910_get_mode,
};
static struct regulator_ops tps65910_ops = {
- .is_enabled = tps65910_is_enabled,
- .enable = tps65910_enable,
- .disable = tps65910_disable,
+ .is_enabled = regulator_is_enabled_regmap,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
.enable_time = tps65910_enable_time,
.set_mode = tps65910_set_mode,
.get_mode = tps65910_get_mode,
- .get_voltage = tps65910_get_voltage,
+ .get_voltage_sel = tps65910_get_voltage_sel,
.set_voltage_sel = tps65910_set_voltage_sel,
.list_voltage = tps65910_list_voltage,
};
static struct regulator_ops tps65911_ops = {
- .is_enabled = tps65910_is_enabled,
- .enable = tps65910_enable,
- .disable = tps65910_disable,
+ .is_enabled = regulator_is_enabled_regmap,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
.enable_time = tps65910_enable_time,
.set_mode = tps65910_set_mode,
.get_mode = tps65910_get_mode,
- .get_voltage = tps65911_get_voltage,
+ .get_voltage_sel = tps65911_get_voltage_sel,
.set_voltage_sel = tps65911_set_voltage_sel,
.list_voltage = tps65911_list_voltage,
};
return ret;
}
+#ifdef CONFIG_OF
+
+static struct of_regulator_match tps65910_matches[] = {
+ { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
+ { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
+ { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
+ { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
+ { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
+ { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
+ { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
+ { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
+ { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
+ { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
+ { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
+ { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
+ { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
+};
+
+static struct of_regulator_match tps65911_matches[] = {
+ { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
+ { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
+ { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
+ { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
+ { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
+ { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
+ { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
+ { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
+ { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
+ { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
+ { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
+ { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
+ { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
+};
+
+static struct tps65910_board *tps65910_parse_dt_reg_data(
+ struct platform_device *pdev,
+ struct of_regulator_match **tps65910_reg_matches)
+{
+ struct tps65910_board *pmic_plat_data;
+ struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
+ struct device_node *np = pdev->dev.parent->of_node;
+ struct device_node *regulators;
+ struct of_regulator_match *matches;
+ unsigned int prop;
+ int idx = 0, ret, count;
+
+ pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
+ GFP_KERNEL);
+
+ if (!pmic_plat_data) {
+ dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n");
+ return NULL;
+ }
+
+ regulators = of_find_node_by_name(np, "regulators");
+ if (!regulators) {
+ dev_err(&pdev->dev, "regulator node not found\n");
+ return NULL;
+ }
+
+ switch (tps65910_chip_id(tps65910)) {
+ case TPS65910:
+ count = ARRAY_SIZE(tps65910_matches);
+ matches = tps65910_matches;
+ break;
+ case TPS65911:
+ count = ARRAY_SIZE(tps65911_matches);
+ matches = tps65911_matches;
+ break;
+ default:
+ dev_err(&pdev->dev, "Invalid tps chip version\n");
+ return NULL;
+ }
+
+ ret = of_regulator_match(pdev->dev.parent, regulators, matches, count);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
+ ret);
+ return NULL;
+ }
+
+ *tps65910_reg_matches = matches;
+
+ for (idx = 0; idx < count; idx++) {
+ if (!matches[idx].init_data || !matches[idx].of_node)
+ continue;
+
+ pmic_plat_data->tps65910_pmic_init_data[idx] =
+ matches[idx].init_data;
+
+ ret = of_property_read_u32(matches[idx].of_node,
+ "ti,regulator-ext-sleep-control", &prop);
+ if (!ret)
+ pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
+ }
+
+ return pmic_plat_data;
+}
+#else
+static inline struct tps65910_board *tps65910_parse_dt_reg_data(
+ struct platform_device *pdev,
+ struct of_regulator_match **tps65910_reg_matches)
+{
+ *tps65910_reg_matches = NULL;
+ return 0;
+}
+#endif
+
static __devinit int tps65910_probe(struct platform_device *pdev)
{
struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
+ struct regulator_config config = { };
struct tps_info *info;
struct regulator_init_data *reg_data;
struct regulator_dev *rdev;
struct tps65910_reg *pmic;
struct tps65910_board *pmic_plat_data;
+ struct of_regulator_match *tps65910_reg_matches = NULL;
int i, err;
pmic_plat_data = dev_get_platdata(tps65910->dev);
- if (!pmic_plat_data)
+ if (!pmic_plat_data && tps65910->dev->of_node)
+ pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
+ &tps65910_reg_matches);
+
+ if (!pmic_plat_data) {
+ dev_err(&pdev->dev, "Platform data not found\n");
return -EINVAL;
+ }
- pmic = kzalloc(sizeof(*pmic), GFP_KERNEL);
- if (!pmic)
+ pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
+ if (!pmic) {
+ dev_err(&pdev->dev, "Memory allocation failed for pmic\n");
return -ENOMEM;
+ }
mutex_init(&pmic->mutex);
pmic->mfd = tps65910;
info = tps65911_regs;
break;
default:
- pr_err("Invalid tps chip version\n");
- kfree(pmic);
+ dev_err(&pdev->dev, "Invalid tps chip version\n");
return -ENODEV;
}
- pmic->desc = kcalloc(pmic->num_regulators,
+ pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators *
sizeof(struct regulator_desc), GFP_KERNEL);
if (!pmic->desc) {
- err = -ENOMEM;
- goto err_free_pmic;
+ dev_err(&pdev->dev, "Memory alloc fails for desc\n");
+ return -ENOMEM;
}
- pmic->info = kcalloc(pmic->num_regulators,
+ pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators *
sizeof(struct tps_info *), GFP_KERNEL);
if (!pmic->info) {
- err = -ENOMEM;
- goto err_free_desc;
+ dev_err(&pdev->dev, "Memory alloc fails for info\n");
+ return -ENOMEM;
}
- pmic->rdev = kcalloc(pmic->num_regulators,
+ pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators *
sizeof(struct regulator_dev *), GFP_KERNEL);
if (!pmic->rdev) {
- err = -ENOMEM;
- goto err_free_info;
+ dev_err(&pdev->dev, "Memory alloc fails for rdev\n");
+ return -ENOMEM;
}
for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
pmic->desc[i].type = REGULATOR_VOLTAGE;
pmic->desc[i].owner = THIS_MODULE;
+ pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
+ pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
+
+ config.dev = tps65910->dev;
+ config.init_data = reg_data;
+ config.driver_data = pmic;
+ config.regmap = tps65910->regmap;
+
+ if (tps65910_reg_matches)
+ config.of_node = tps65910_reg_matches[i].of_node;
- rdev = regulator_register(&pmic->desc[i],
- tps65910->dev, reg_data, pmic, NULL);
+ rdev = regulator_register(&pmic->desc[i], &config);
if (IS_ERR(rdev)) {
dev_err(tps65910->dev,
"failed to register %s regulator\n",
err_unregister_regulator:
while (--i >= 0)
regulator_unregister(pmic->rdev[i]);
- kfree(pmic->rdev);
-err_free_info:
- kfree(pmic->info);
-err_free_desc:
- kfree(pmic->desc);
-err_free_pmic:
- kfree(pmic);
return err;
}
for (i = 0; i < pmic->num_regulators; i++)
regulator_unregister(pmic->rdev[i]);
- kfree(pmic->rdev);
- kfree(pmic->info);
- kfree(pmic->desc);
- kfree(pmic);
return 0;
}
{
struct rproc *rproc = rvdev->rproc;
- for (i--; i > 0; i--) {
+ for (i--; i >= 0; i--) {
struct rproc_vring *rvring = &rvdev->vring[i];
int size = PAGE_ALIGN(vring_size(rvring->len, rvring->align));
goto out;
out:
- if (fw)
- release_firmware(fw);
+ release_firmware(fw);
/* allow rproc_unregister() contexts, if any, to proceed */
complete_all(&rproc->firmware_loading_complete);
}
continue;
/* Attempt a retry. */
status = 1;
- } else
+ } else {
status = qla2x00_fabric_login(vha,
fcport, &next_loopid);
+ if (status == QLA_SUCCESS) {
+ int status2;
+ uint8_t opts;
+
+ opts = 0;
+ if (fcport->flags &
+ FCF_FCP2_DEVICE)
+ opts |= BIT_1;
+ status2 =
+ qla2x00_get_port_database(
+ vha, fcport,
+ opts);
+ if (status2 != QLA_SUCCESS)
+ status = 1;
+ }
+ }
} else
status = qla2x00_local_device_login(vha,
fcport);
mutex_lock(&qla_fw_lock);
for (idx = 0; idx < FW_BLOBS; idx++)
- if (qla_fw_blobs[idx].fw)
- release_firmware(qla_fw_blobs[idx].fw);
+ release_firmware(qla_fw_blobs[idx].fw);
mutex_unlock(&qla_fw_lock);
}
}
/**
- * scsi_eh_prep_cmnd - Save a scsi command info as part of error recory
+ * scsi_eh_prep_cmnd - Save a scsi command info as part of error recovery
* @scmd: SCSI command structure to hijack
* @ses: structure to save restore information
* @cmnd: CDB to send. Can be NULL if no new cmnd is needed
EXPORT_SYMBOL(scsi_eh_prep_cmnd);
/**
- * scsi_eh_restore_cmnd - Restore a scsi command info as part of error recory
+ * scsi_eh_restore_cmnd - Restore a scsi command info as part of error recovery
* @scmd: SCSI command structure to restore
* @ses: saved information from a coresponding call to scsi_eh_prep_cmnd
*
EXPORT_SYMBOL(scsi_eh_restore_cmnd);
/**
- * scsi_send_eh_cmnd - submit a scsi command as part of error recory
+ * scsi_send_eh_cmnd - submit a scsi command as part of error recovery
* @scmd: SCSI command structure to hijack
* @cmnd: CDB to send
* @cmnd_size: size in bytes of @cmnd
scsi_eh_restore_cmnd(scmd, &ses);
- if (sdrv->eh_action)
+ if (sdrv && sdrv->eh_action)
rtn = sdrv->eh_action(scmd, cmnd, cmnd_size, rtn);
return rtn;
* (and thus for each /dev/ node).
*/
struct gs_port {
+ struct tty_port port;
spinlock_t port_lock; /* guard port_* access */
struct gserial *port_usb;
- struct tty_struct *port_tty;
- unsigned open_count;
bool openclose; /* open/close in progress */
u8 port_num;
- wait_queue_head_t close_wait; /* wait for last close */
-
struct list_head read_pool;
int read_started;
int read_allocated;
break;
}
- if (do_tty_wake && port->port_tty)
- tty_wakeup(port->port_tty);
+ if (do_tty_wake && port->port.tty)
+ tty_wakeup(port->port.tty);
return status;
}
struct tty_struct *tty;
/* no more rx if closed */
- tty = port->port_tty;
+ tty = port->port.tty;
if (!tty)
break;
/* hand any queued data to the tty */
spin_lock_irq(&port->port_lock);
- tty = port->port_tty;
+ tty = port->port.tty;
while (!list_empty(queue)) {
struct usb_request *req;
/* unblock any pending writes into our circular buffer */
if (started) {
- tty_wakeup(port->port_tty);
+ tty_wakeup(port->port.tty);
} else {
gs_free_requests(ep, head, &port->read_allocated);
gs_free_requests(port->port_usb->in, &port->write_pool,
spin_lock_irq(&port->port_lock);
/* already open? Great. */
- if (port->open_count) {
+ if (port->port.count) {
status = 0;
- port->open_count++;
+ port->port.count++;
/* currently opening/closing? wait ... */
} else if (port->openclose) {
/* REVISIT maybe wait for "carrier detect" */
tty->driver_data = port;
- port->port_tty = tty;
+ port->port.tty = tty;
- port->open_count = 1;
+ port->port.count = 1;
port->openclose = false;
/* if connected, start the I/O stream */
spin_lock_irq(&port->port_lock);
- if (port->open_count != 1) {
- if (port->open_count == 0)
+ if (port->port.count != 1) {
+ if (port->port.count == 0)
WARN_ON(1);
else
- --port->open_count;
+ --port->port.count;
goto exit;
}
* and sleep if necessary
*/
port->openclose = true;
- port->open_count = 0;
+ port->port.count = 0;
gser = port->port_usb;
if (gser && gser->disconnect)
gs_buf_clear(&port->port_write_buf);
tty->driver_data = NULL;
- port->port_tty = NULL;
+ port->port.tty = NULL;
port->openclose = false;
pr_debug("gs_close: ttyGS%d (%p,%p) done!\n",
port->port_num, tty, file);
- wake_up_interruptible(&port->close_wait);
+ wake_up_interruptible(&port->port.close_wait);
exit:
spin_unlock_irq(&port->port_lock);
}
unsigned long flags;
int status;
- pr_vdebug("gs_put_char: (%d,%p) char=0x%x, called from %p\n",
+ pr_vdebug("gs_put_char: (%d,%p) char=0x%x, called from %pf\n",
port->port_num, tty, ch, __builtin_return_address(0));
spin_lock_irqsave(&port->port_lock, flags);
static struct tty_driver *gs_tty_driver;
-static int __init
+static int
gs_port_alloc(unsigned port_num, struct usb_cdc_line_coding *coding)
{
struct gs_port *port;
if (port == NULL)
return -ENOMEM;
+ tty_port_init(&port->port);
spin_lock_init(&port->port_lock);
- init_waitqueue_head(&port->close_wait);
init_waitqueue_head(&port->drain_wait);
tasklet_init(&port->push, gs_rx_push, (unsigned long) port);
*
* Returns negative errno or zero.
*/
-int __init gserial_setup(struct usb_gadget *g, unsigned count)
+int gserial_setup(struct usb_gadget *g, unsigned count)
{
unsigned i;
struct usb_cdc_line_coding coding;
int cond;
spin_lock_irq(&port->port_lock);
- cond = (port->open_count == 0) && !port->openclose;
+ cond = (port->port.count == 0) && !port->openclose;
spin_unlock_irq(&port->port_lock);
return cond;
}
tasklet_kill(&port->push);
/* wait for old opens to finish */
- wait_event(port->close_wait, gs_closed(port));
+ wait_event(port->port.close_wait, gs_closed(port));
WARN_ON(port->port_usb != NULL);
/* if it's already open, start I/O ... and notify the serial
* protocol about open/close status (connect/disconnect).
*/
- if (port->open_count) {
+ if (port->port.count) {
pr_debug("gserial_connect: start ttyGS%d\n", port->port_num);
gs_start_io(port);
if (gser->connect)
port->port_usb = NULL;
gser->ioport = NULL;
- if (port->open_count > 0 || port->openclose) {
+ if (port->port.count > 0 || port->openclose) {
wake_up_interruptible(&port->drain_wait);
- if (port->port_tty)
- tty_hangup(port->port_tty);
+ if (port->port.tty)
+ tty_hangup(port->port.tty);
}
spin_unlock_irqrestore(&port->port_lock, flags);
/* finally, free any unused/unusable I/O buffers */
spin_lock_irqsave(&port->port_lock, flags);
- if (port->open_count == 0 && !port->openclose)
+ if (port->port.count == 0 && !port->openclose)
gs_buf_free(&port->port_write_buf);
gs_free_requests(gser->out, &port->read_pool, NULL);
gs_free_requests(gser->out, &port->read_queue, NULL);
config USB_EHCI_ROOT_HUB_TT
bool "Root Hub Transaction Translators"
- depends on USB_EHCI_HCD
+ depends on USB_EHCI_HCD || USB_CHIPIDEA_HOST
---help---
Some EHCI chips have vendor-specific extensions to integrate
transaction translators, so that no OHCI or UHCI companion
config USB_EHCI_TT_NEWSCHED
bool "Improved Transaction Translator scheduling"
- depends on USB_EHCI_HCD
+ depends on USB_EHCI_HCD || USB_CHIPIDEA_HOST
default y
---help---
This changes the periodic scheduling code to fill more of the low
depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \
ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
PPC_MPC512x || CPU_CAVIUM_OCTEON || \
- PMC_MSP || SPARC_LEON)
+ PMC_MSP || SPARC_LEON || MIPS_SEAD3)
default y
config USB_EHCI_BIG_ENDIAN_DESC
bool
depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
- PPC_MPC512x || PMC_MSP || SPARC_LEON)
+ PPC_MPC512x || PMC_MSP || SPARC_LEON || \
+ MIPS_SEAD3)
default y
config XPS_USB_HCD_XILINX
bool "EHCI support for OMAP3 and later chips"
depends on USB_EHCI_HCD && ARCH_OMAP
default y
- --- help ---
+ ---help---
Enables support for the on-chip EHCI controller on
OMAP3 and later chips.
depends on USB && USB_ARCH_HAS_OHCI
select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
select USB_OTG_UTILS if ARCH_OMAP
+ select USB_ISP1301 if ARCH_LPC32XX || ARCH_PNX4008
---help---
The Open Host Controller Interface (OHCI) is a standard for accessing
USB 1.1 host controller hardware. It does more in hardware than Intel's
If unsure, say Y.
config USB_OHCI_HCD_SSB
- bool "OHCI support for Broadcom SSB OHCI core"
+ bool "OHCI support for Broadcom SSB OHCI core (DEPRECATED)"
depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL
+ select USB_HCD_SSB
+ select USB_OHCI_HCD_PLATFORM
default n
---help---
+ This option is deprecated now and the driver was removed, use
+ USB_HCD_SSB and USB_OHCI_HCD_PLATFORM instead.
+
Support for the Sonics Silicon Backplane (SSB) attached
Broadcom USB OHCI core.
config USB_OCTEON2_COMMON
bool
default y if USB_OCTEON_EHCI || USB_OCTEON_OHCI
+
+config USB_HCD_BCMA
+ tristate "BCMA usb host driver"
+ depends on BCMA && EXPERIMENTAL
+ select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD
+ select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD
+ help
+ Enbale support for the EHCI and OCHI host controller on an bcma bus.
+ It converts the bcma driver into two platform device drivers
+ for ehci and ohci.
+
+ If unsure, say N.
+
+config USB_HCD_SSB
+ tristate "SSB usb host driver"
+ depends on SSB && EXPERIMENTAL
+ select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD
+ select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD
+ help
+ Enbale support for the EHCI and OCHI host controller on an bcma bus.
+ It converts the bcma driver into two platform device drivers
+ for ehci and ohci.
+
+ If unsure, say N.
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
US_FL_IGNORE_RESIDUE ),
- /* Deduced by Jonathan Woithe <jwoithe@physics.adelaide.edu.au>
+ /* Deduced by Jonathan Woithe <jwoithe@just42.net>
* Entry needed for flags: US_FL_FIX_INQUIRY because initial inquiry message
* always fails and confuses drive.
*/
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
US_FL_IGNORE_RESIDUE ),
+/* Reported by Jesse Feddema <jdfeddema@gmail.com> */
+UNUSUAL_DEV( 0x177f, 0x0400, 0x0000, 0x0000,
+ "Yarvik",
+ "PMP400",
+ USB_SC_DEVICE, USB_PR_DEVICE, NULL,
+ US_FL_BULK_IGNORE_TAG | US_FL_MAX_SECTORS_64 ),
+
/* Reported by Hans de Goede <hdegoede@redhat.com>
* These Appotech controllers are found in Picture Frames, they provide a
* (buggy) emulation of a cdrom drive which contains the windows software
au1100fb_fix.mmio_start = regs_res->start;
au1100fb_fix.mmio_len = resource_size(regs_res);
- if (!devm_request_mem_region(au1100fb_fix.mmio_start,
+ if (!devm_request_mem_region(&dev->dev,
+ au1100fb_fix.mmio_start,
au1100fb_fix.mmio_len,
DRIVER_NAME)) {
print_err("fail to lock memory region at 0x%08lx",
fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
(fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
- fbdev->fb_mem = dmam_alloc_coherent(&dev->dev, &dev->dev,
+ fbdev->fb_mem = dmam_alloc_coherent(&dev->dev,
PAGE_ALIGN(fbdev->fb_len),
&fbdev->fb_phys, GFP_KERNEL);
if (!fbdev->fb_mem) {
for (page = (unsigned long)fbdev->fb_mem;
page < PAGE_ALIGN((unsigned long)fbdev->fb_mem + fbdev->fb_len);
page += PAGE_SIZE) {
- #if CONFIG_DMA_NONCOHERENT
+ #ifdef CONFIG_DMA_NONCOHERENT
SetPageReserved(virt_to_page(CAC_ADDR((void *)page)));
#else
SetPageReserved(virt_to_page(page));
tristate "Xen /dev/xen/evtchn device"
default y
help
- The evtchn driver allows a userspace process to triger event
+ The evtchn driver allows a userspace process to trigger event
channels and to receive notification of an event channel
firing.
If in doubt, say yes.
depends on XEN && X86 && ACPI_PROCESSOR && CPU_FREQ
default m
help
- This ACPI processor uploads Power Management information to the Xen hypervisor.
-
- To do that the driver parses the Power Management data and uploads said
- information to the Xen hypervisor. Then the Xen hypervisor can select the
- proper Cx and Pxx states. It also registers itslef as the SMM so that
- other drivers (such as ACPI cpufreq scaling driver) will not load.
-
- To compile this driver as a module, choose M here: the
- module will be called xen_acpi_processor If you do not know what to choose,
- select M here. If the CPUFREQ drivers are built in, select Y here.
+ This ACPI processor uploads Power Management information to the Xen
+ hypervisor.
+
+ To do that the driver parses the Power Management data and uploads
+ said information to the Xen hypervisor. Then the Xen hypervisor can
+ select the proper Cx and Pxx states. It also registers itslef as the
+ SMM so that other drivers (such as ACPI cpufreq scaling driver) will
+ not load.
+
+ To compile this driver as a module, choose M here: the module will be
+ called xen_acpi_processor If you do not know what to choose, select
+ M here. If the CPUFREQ drivers are built in, select Y here.
endmenu
* in the wrong place.
*/
static int verify_parent_transid(struct extent_io_tree *io_tree,
- struct extent_buffer *eb, u64 parent_transid)
+ struct extent_buffer *eb, u64 parent_transid,
+ int atomic)
{
struct extent_state *cached_state = NULL;
int ret;
if (!parent_transid || btrfs_header_generation(eb) == parent_transid)
return 0;
+ if (atomic)
+ return -EAGAIN;
+
lock_extent_bits(io_tree, eb->start, eb->start + eb->len - 1,
0, &cached_state);
if (extent_buffer_uptodate(eb) &&
ret = read_extent_buffer_pages(io_tree, eb, start,
WAIT_COMPLETE,
btree_get_extent, mirror_num);
- if (!ret && !verify_parent_transid(io_tree, eb, parent_transid))
+ if (!ret && !verify_parent_transid(io_tree, eb,
+ parent_transid, 0))
break;
/*
if (test_bit(EXTENT_BUFFER_CORRUPT, &eb->bflags))
break;
- if (!failed_mirror) {
- failed = 1;
- printk(KERN_ERR "failed mirror was %d\n", eb->failed_mirror);
- failed_mirror = eb->failed_mirror;
- }
-
num_copies = btrfs_num_copies(&root->fs_info->mapping_tree,
eb->start, eb->len);
if (num_copies == 1)
break;
+ if (!failed_mirror) {
+ failed = 1;
+ failed_mirror = eb->read_mirror;
+ }
+
mirror_num++;
if (mirror_num == failed_mirror)
mirror_num++;
}
static int btree_readpage_end_io_hook(struct page *page, u64 start, u64 end,
- struct extent_state *state)
+ struct extent_state *state, int mirror)
{
struct extent_io_tree *tree;
u64 found_start;
if (!reads_done)
goto err;
+ eb->read_mirror = mirror;
if (test_bit(EXTENT_BUFFER_IOERR, &eb->bflags)) {
ret = -EIO;
goto err;
eb = (struct extent_buffer *)page->private;
set_bit(EXTENT_BUFFER_IOERR, &eb->bflags);
- eb->failed_mirror = failed_mirror;
+ eb->read_mirror = failed_mirror;
if (test_and_clear_bit(EXTENT_BUFFER_READAHEAD, &eb->bflags))
btree_readahead_hook(root, eb, eb->start, -EIO);
return -EIO; /* we fixed nothing */
root->commit_root = NULL;
root->node = read_tree_block(root, btrfs_root_bytenr(&root->root_item),
blocksize, generation);
- if (!root->node || !btrfs_buffer_uptodate(root->node, generation)) {
+ if (!root->node || !btrfs_buffer_uptodate(root->node, generation, 0)) {
free_extent_buffer(root->node);
root->node = NULL;
return -EIO;
goto fail_sb_buffer;
}
- if (sectorsize < PAGE_SIZE) {
- printk(KERN_WARNING "btrfs: Incompatible sector size "
- "found on %s\n", sb->s_id);
+ if (sectorsize != PAGE_SIZE) {
+ printk(KERN_WARNING "btrfs: Incompatible sector size(%lu) "
+ "found on %s\n", (unsigned long)sectorsize, sb->s_id);
goto fail_sb_buffer;
}
* one reference for us, and we leave it for the
* caller
*/
- device->flush_bio = NULL;;
+ device->flush_bio = NULL;
bio = bio_alloc(GFP_NOFS, 0);
if (!bio)
return -ENOMEM;
return 0;
}
-int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid)
+int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid,
+ int atomic)
{
int ret;
struct inode *btree_inode = buf->pages[0]->mapping->host;
return ret;
ret = verify_parent_transid(&BTRFS_I(btree_inode)->io_tree, buf,
- parent_transid);
+ parent_transid, atomic);
+ if (ret == -EAGAIN)
+ return ret;
return !ret;
}
#define TCP_THIN_LINEAR_TIMEOUTS 16 /* Use linear timeouts for thin streams*/
#define TCP_THIN_DUPACK 17 /* Fast retrans. after 1 dupack */
#define TCP_USER_TIMEOUT 18 /* How long for loss retry before timeout */
+#define TCP_REPAIR 19 /* TCP sock is under repair right now */
+#define TCP_REPAIR_QUEUE 20
+#define TCP_QUEUE_SEQ 21
+#define TCP_REPAIR_OPTIONS 22
+
+struct tcp_repair_opt {
+ __u32 opt_code;
+ __u32 opt_val;
+};
+
+enum {
+ TCP_NO_QUEUE,
+ TCP_RECV_QUEUE,
+ TCP_SEND_QUEUE,
+ TCP_QUEUES_NR,
+};
/* for TCP_INFO socket option */
#define TCPI_OPT_TIMESTAMPS 1
u8 nonagle : 4,/* Disable Nagle algorithm? */
thin_lto : 1,/* Use linear timeouts for thin streams */
thin_dupack : 1,/* Fast retransmit on first dupack */
- unused : 2;
+ repair : 1,
+ unused : 1;
+ u8 repair_queue;
+ u8 do_early_retrans:1,/* Enable RFC5827 early-retransmit */
+ early_retrans_delayed:1; /* Delayed ER timer installed */
/* RTT measurement */
u32 srtt; /* smoothed round trip time << 3 */
struct sk_buff_head out_of_order_queue; /* Out of order segments go here */
- /* SACKs data, these 2 need to be together (see tcp_build_and_update_options) */
+ /* SACKs data, these 2 need to be together (see tcp_options_write) */
struct tcp_sack_block duplicate_sack[1]; /* D-SACK block */
struct tcp_sack_block selective_acks[4]; /* The SACKS themselves*/
config FUNCTION_TRACER
bool "Kernel Function Tracer"
depends on HAVE_FUNCTION_TRACER
- select FRAME_POINTER if !ARM_UNWIND && !PPC && !S390 && !MICROBLAZE
select KALLSYMS
select GENERIC_TRACER
select CONTEXT_SWITCH_TRACER
bool "Trace likely/unlikely profiler"
select TRACE_BRANCH_PROFILING
help
- This tracer profiles all the the likely and unlikely macros
+ This tracer profiles all likely and unlikely macros
in the kernel. It will display the results in:
/sys/kernel/debug/tracing/trace_stat/branch_annotated
* frames.
*
* 1. Dix Ethernet EtherType frames encoded by placing EtherType
- * field in h_type field. Data follows immediatelly after header.
+ * field in h_type field. Data follows immediately after header.
* 2. LLC Data frames whose total length, including LLC field and data,
* but not padding required to meet the minimum data frame length,
* is less than 1536(0x0600) MUST be encoded by placing that length
- * in the h_type field. The LLC field follows header immediatelly.
+ * in the h_type field. The LLC field follows header immediately.
* 3. LLC data frames longer than this maximum MUST be encoded by placing
* the value 0 in the h_type field.
*
int itfnum; /* e.g. 2 for lec2, 5 for lec5 */
struct lane2_ops *lane2_ops; /* can be NULL for LANE v1 */
int is_proxy; /* bridge between ATM and Ethernet */
- int is_trdev; /* Device type, 0 = Ethernet, 1 = TokenRing */
};
struct lec_vcc_priv {
* Copyright (c) 2004 Kailang Yang <kailang@realtek.com.tw>
* PeiSen Hou <pshou@realtek.com.tw>
* Takashi Iwai <tiwai@suse.de>
- * Jonathan Woithe <jwoithe@physics.adelaide.edu.au>
+ * Jonathan Woithe <jwoithe@just42.net>
*
* This driver is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
ALC_FIXUP_ACT_BUILD,
};
+static void alc_apply_pincfgs(struct hda_codec *codec,
+ const struct alc_pincfg *cfg)
+{
+ for (; cfg->nid; cfg++)
+ snd_hda_codec_set_pincfg(codec, cfg->nid, cfg->val);
+}
+
static void alc_apply_fixup(struct hda_codec *codec, int action)
{
struct alc_spec *spec = codec->spec;
snd_printdd(KERN_INFO "hda_codec: %s: "
"Apply pincfg for %s\n",
codec->chip_name, modelname);
- for (; cfg->nid; cfg++)
- snd_hda_codec_set_pincfg(codec, cfg->nid,
- cfg->val);
+ alc_apply_pincfgs(codec, cfg);
break;
case ALC_FIXUP_VERBS:
if (action != ALC_FIXUP_ACT_PROBE || !fix->v.verbs)
for (;;) {
badness = fill_and_eval_dacs(codec, fill_hardwired,
fill_mio_first);
- if (badness < 0)
+ if (badness < 0) {
+ kfree(best_cfg);
return badness;
+ }
debug_badness("==> lo_type=%d, wired=%d, mio=%d, badness=0x%x\n",
cfg->line_out_type, fill_hardwired, fill_mio_first,
badness);
cfg->line_out_type = AUTO_PIN_SPEAKER_OUT;
fill_hardwired = true;
continue;
- }
+ }
if (cfg->hp_outs > 0 &&
cfg->line_out_type == AUTO_PIN_SPEAKER_OUT) {
cfg->speaker_outs = cfg->line_outs;
cfg->line_out_type = AUTO_PIN_HP_OUT;
fill_hardwired = true;
continue;
- }
+ }
break;
}
static int alc880_parse_auto_config(struct hda_codec *codec)
{
static const hda_nid_t alc880_ignore[] = { 0x1d, 0 };
- static const hda_nid_t alc880_ssids[] = { 0x15, 0x1b, 0x14, 0 };
+ static const hda_nid_t alc880_ssids[] = { 0x15, 0x1b, 0x14, 0 };
return alc_parse_auto_config(codec, alc880_ignore, alc880_ssids);
}
ALC260_FIXUP_GPIO1_TOGGLE,
ALC260_FIXUP_REPLACER,
ALC260_FIXUP_HP_B1900,
+ ALC260_FIXUP_KN1,
};
static void alc260_gpio1_automute(struct hda_codec *codec)
}
}
+static void alc260_fixup_kn1(struct hda_codec *codec,
+ const struct alc_fixup *fix, int action)
+{
+ struct alc_spec *spec = codec->spec;
+ static const struct alc_pincfg pincfgs[] = {
+ { 0x0f, 0x02214000 }, /* HP/speaker */
+ { 0x12, 0x90a60160 }, /* int mic */
+ { 0x13, 0x02a19000 }, /* ext mic */
+ { 0x18, 0x01446000 }, /* SPDIF out */
+ /* disable bogus I/O pins */
+ { 0x10, 0x411111f0 },
+ { 0x11, 0x411111f0 },
+ { 0x14, 0x411111f0 },
+ { 0x15, 0x411111f0 },
+ { 0x16, 0x411111f0 },
+ { 0x17, 0x411111f0 },
+ { 0x19, 0x411111f0 },
+ { }
+ };
+
+ switch (action) {
+ case ALC_FIXUP_ACT_PRE_PROBE:
+ alc_apply_pincfgs(codec, pincfgs);
+ break;
+ case ALC_FIXUP_ACT_PROBE:
+ spec->init_amp = ALC_INIT_NONE;
+ break;
+ }
+}
+
static const struct alc_fixup alc260_fixups[] = {
[ALC260_FIXUP_HP_DC5750] = {
.type = ALC_FIXUP_PINS,
.v.func = alc260_fixup_gpio1_toggle,
.chained = true,
.chain_id = ALC260_FIXUP_COEF,
- }
+ },
+ [ALC260_FIXUP_KN1] = {
+ .type = ALC_FIXUP_FUNC,
+ .v.func = alc260_fixup_kn1,
+ },
};
static const struct snd_pci_quirk alc260_fixup_tbl[] = {
SND_PCI_QUIRK(0x103c, 0x280a, "HP dc5750", ALC260_FIXUP_HP_DC5750),
SND_PCI_QUIRK(0x103c, 0x30ba, "HP Presario B1900", ALC260_FIXUP_HP_B1900),
SND_PCI_QUIRK(0x1509, 0x4540, "Favorit 100XS", ALC260_FIXUP_GPIO1),
+ SND_PCI_QUIRK(0x152d, 0x0729, "Quanta KN1", ALC260_FIXUP_KN1),
SND_PCI_QUIRK(0x161f, 0x2057, "Replacer 672V", ALC260_FIXUP_REPLACER),
SND_PCI_QUIRK(0x1631, 0xc017, "PB V7900", ALC260_FIXUP_COEF),
{}
{ 0x16, 0x99130111 }, /* CLFE speaker */
{ 0x17, 0x99130112 }, /* surround speaker */
{ }
- }
+ },
+ .chained = true,
+ .chain_id = ALC882_FIXUP_GPIO1,
},
[ALC882_FIXUP_ACER_ASPIRE_8930G] = {
.type = ALC_FIXUP_PINS,
{ 0x20, AC_VERB_SET_COEF_INDEX, 0x07 },
{ 0x20, AC_VERB_SET_PROC_COEF, 0x3050 },
{ }
- }
+ },
+ .chained = true,
+ .chain_id = ALC882_FIXUP_GPIO1,
},
[ALC885_FIXUP_MACPRO_GPIO] = {
.type = ALC_FIXUP_FUNC,
SND_PCI_QUIRK(0x1025, 0x0142, "Acer Aspire 7730G",
ALC882_FIXUP_ACER_ASPIRE_4930G),
SND_PCI_QUIRK(0x1025, 0x0155, "Packard-Bell M5120", ALC882_FIXUP_PB_M5210),
+ SND_PCI_QUIRK(0x1025, 0x021e, "Acer Aspire 5739G",
+ ALC882_FIXUP_ACER_ASPIRE_4930G),
SND_PCI_QUIRK(0x1025, 0x0259, "Acer Aspire 5935", ALC889_FIXUP_DAC_ROUTE),
+ SND_PCI_QUIRK(0x1025, 0x026b, "Acer Aspire 8940G", ALC882_FIXUP_ACER_ASPIRE_8930G),
SND_PCI_QUIRK(0x1025, 0x0296, "Acer Aspire 7736z", ALC882_FIXUP_ACER_ASPIRE_7736),
SND_PCI_QUIRK(0x1043, 0x13c2, "Asus A7M", ALC882_FIXUP_EAPD),
SND_PCI_QUIRK(0x1043, 0x1873, "ASUS W90V", ALC882_FIXUP_ASUS_W90V),
SND_PCI_QUIRK(0x106b, 0x3f00, "Macbook 5,1", ALC889_FIXUP_IMAC91_VREF),
SND_PCI_QUIRK(0x106b, 0x4000, "MacbookPro 5,1", ALC889_FIXUP_IMAC91_VREF),
SND_PCI_QUIRK(0x106b, 0x4100, "Macmini 3,1", ALC889_FIXUP_IMAC91_VREF),
+ SND_PCI_QUIRK(0x106b, 0x4200, "Mac Pro 5,1", ALC885_FIXUP_MACPRO_GPIO),
SND_PCI_QUIRK(0x106b, 0x4600, "MacbookPro 5,2", ALC889_FIXUP_IMAC91_VREF),
SND_PCI_QUIRK(0x106b, 0x4900, "iMac 9,1 Aluminum", ALC889_FIXUP_IMAC91_VREF),
SND_PCI_QUIRK(0x106b, 0x4a00, "Macbook 5,2", ALC889_FIXUP_IMAC91_VREF),
SND_PCI_QUIRK(0x1071, 0x8258, "Evesham Voyaeger", ALC882_FIXUP_EAPD),
+ SND_PCI_QUIRK(0x1462, 0x7350, "MSI-7350", ALC889_FIXUP_CD),
SND_PCI_QUIRK_VENDOR(0x1462, "MSI", ALC882_FIXUP_GPIO3),
SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte EP45-DS3", ALC889_FIXUP_CD),
SND_PCI_QUIRK(0x147b, 0x107a, "Abit AW9D-MAX", ALC882_FIXUP_ABIT_AW9D_MAX),
{}
};
+static const struct alc_model_fixup alc882_fixup_models[] = {
+ {.id = ALC882_FIXUP_ACER_ASPIRE_4930G, .name = "acer-aspire-4930g"},
+ {.id = ALC882_FIXUP_ACER_ASPIRE_8930G, .name = "acer-aspire-8930g"},
+ {.id = ALC883_FIXUP_ACER_EAPD, .name = "acer-aspire"},
+ {}
+};
+
/*
* BIOS auto configuration
*/
if (err < 0)
goto error;
- alc_pick_fixup(codec, NULL, alc882_fixup_tbl, alc882_fixups);
+ alc_pick_fixup(codec, alc882_fixup_models, alc882_fixup_tbl,
+ alc882_fixups);
alc_apply_fixup(codec, ALC_FIXUP_ACT_PRE_PROBE);
alc_auto_parse_customize_define(codec);
snd_hda_codec_write(codec, 0x1a, 0, AC_VERB_SET_PROC_COEF, tmp | 0x80);
}
#endif
- alc_auto_parse_customize_define(codec);
-
alc_fix_pll_init(codec, 0x20, 0x0a, 10);
alc_pick_fixup(codec, NULL, alc262_fixup_tbl, alc262_fixups);
alc_apply_fixup(codec, ALC_FIXUP_ACT_PRE_PROBE);
+ alc_auto_parse_customize_define(codec);
+
/* automatic parse from the BIOS config */
err = alc262_parse_auto_config(codec);
if (err < 0)
static const struct snd_pci_quirk alc269_fixup_tbl[] = {
SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_MIC2_MUTE_LED),
+ SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_DMIC),
SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW),
SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC),
SND_PCI_QUIRK(0x1043, 0x831a, "ASUS P901", ALC269_FIXUP_STEREO_DMIC),
* Basically the device should work as is without the fixup table.
* If BIOS doesn't give a proper info, enable the corresponding
* fixup entry.
- */
+ */
SND_PCI_QUIRK(0x1043, 0x8330, "ASUS Eeepc P703 P900A",
ALC269_FIXUP_AMIC),
SND_PCI_QUIRK(0x1043, 0x1013, "ASUS N61Da", ALC269_FIXUP_AMIC),
spec->mixer_nid = 0x0b;
- alc_auto_parse_customize_define(codec);
-
err = alc_codec_rename_from_preset(codec);
if (err < 0)
goto error;
alc269_fixup_tbl, alc269_fixups);
alc_apply_fixup(codec, ALC_FIXUP_ACT_PRE_PROBE);
+ alc_auto_parse_customize_define(codec);
+
/* automatic parse from the BIOS config */
err = alc269_parse_auto_config(codec);
if (err < 0)
{
if (action == ALC_FIXUP_ACT_PRE_PROBE)
codec->no_jack_detect = 1;
-}
+}
static const struct alc_fixup alc861_fixups[] = {
[ALC861_FIXUP_FSC_AMILO_PI1505] = {
* Basically the device should work as is without the fixup table.
* If BIOS doesn't give a proper info, enable the corresponding
* fixup entry.
- */
+ */
SND_PCI_QUIRK(0x1043, 0x1000, "ASUS N50Vm", ALC662_FIXUP_ASUS_MODE1),
SND_PCI_QUIRK(0x1043, 0x1092, "ASUS NB", ALC662_FIXUP_ASUS_MODE3),
SND_PCI_QUIRK(0x1043, 0x1173, "ASUS K73Jn", ALC662_FIXUP_ASUS_MODE1),
/* handle multiple HPs as is */
spec->parse_flags = HDA_PINCFG_NO_HP_FIXUP;
- alc_auto_parse_customize_define(codec);
-
alc_fix_pll_init(codec, 0x20, 0x04, 15);
err = alc_codec_rename_from_preset(codec);
alc_pick_fixup(codec, alc662_fixup_models,
alc662_fixup_tbl, alc662_fixups);
alc_apply_fixup(codec, ALC_FIXUP_ACT_PRE_PROBE);
+
+ alc_auto_parse_customize_define(codec);
+
/* automatic parse from the BIOS config */
err = alc662_parse_auto_config(codec);
if (err < 0)
projects / firefly-linux-kernel-4.4.55.git / commitdiff