Adds comments for dmb approach (acquire loads and RMW load parts are not a problem...

diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index cae2105bcf648064fa57b3f8b00f0407d2dba43f..8f7d914a23b6051a4cff24b2ab47c72ed00c6d9f 100644 (file)
--- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1524,7 +1524,13 @@ bool AArch64LoadStoreOpt::tryToMergeLdStInst(
   return false;
 }
 
-static bool isLoad(MachineInstr* MI) {
+// XXX-comments: Returns true if this is a "normal" load, which refers to loads
+// that relaxed loads will be compiled to. This function is useful when we want
+// to extend the effect of a 'dmb ld' fence to subsequent stores (in the same
+// BB) that has not been interrupted by relaxed loads. Note that acquire loads
+// will be compiled to LDA*, and the load part of RMWs will be compiled to LDAX*
+// or LDX*, which would be in a different basic block.
+static bool isNormalLoad(MachineInstr* MI) {
   switch (MI->getOpcode()) {
     default: { return false; }
     case AArch64::LDRBBpost:
@@ -1688,7 +1694,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
         DEBUG(dbgs() << "Added barrier instruction\n\t" << *DMBInst
                      << "\n\tfor " << *MI << "\n");
         // Skip all the way till we reach the end of the basic block or a load.
-        while (MBBI != E && !isLoad(&*MBBI) && !isBranch(MBBI)) {
+        while (MBBI != E && !isNormalLoad(&*MBBI) && !isBranch(MBBI)) {
           MBBI++;
         }
         break;