Add reg-reg and pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 0b8ab46da4a690fae2e2c9f56fa3b82e1ddb818a..99e6c1b77af36df526f48d29fcedf91ccd5295fa 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -69,6 +69,14 @@ def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
                      [(set GR64:$dst, (add GR64:$src1, imm:$src2)),
                       (implicit PSW)]>;
 
+let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
+// FIXME: Provide proper encoding!
+def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+                     "ngr\t{$dst, $src2}",
+                     [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
+}
+// FIXME: provide patterns for masked and-with-imm
+
 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 // FIXME: Provide proper encoding!
 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),

diff --git a/test/CodeGen/SystemZ/02-RetAnd.ll b/test/CodeGen/SystemZ/02-RetAnd.ll
new file mode 100644 (file)
index 0000000..e174d07
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAnd.ll
@@ -0,0 +1,7 @@
+; RUN: llvm-as < %s | llc
+
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = and i64 %a, %b
+    ret i64 %c
+}
\ No newline at end of file

diff --git a/test/CodeGen/SystemZ/02-RetAndImm.ll b/test/CodeGen/SystemZ/02-RetAndImm.ll
new file mode 100644 (file)
index 0000000..5753723
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAndImm.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = and i64 %a, 1
+    ret i64 %c
+}
+
+; FIXME: SystemZ has 4 and reg-imm instructions depending on imm,
+; we need to support them someday.
\ No newline at end of file