Fix an obvious typo which inverted an immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118951 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 965ec6e4d1cff578c32d3ac011d31ebeaf3daafe..f30fd94a8e1c48bdc0b1d655f0569971b2c3cc96 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1791,7 +1791,7 @@ SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
     return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::t2MOVCCi : ARM::t2MOVCCi16),
                                 MVT::i32, Ops, 5);
   } else if (is_t2_so_imm_not(TrueImm)) {
-    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
+    SDValue True = CurDAG->getTargetConstant(~TrueImm, MVT::i32);
     SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
     SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
     return CurDAG->SelectNodeTo(N, ARM::t2MVNCCi, MVT::i32, Ops, 5);

diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll
index 66e025e3f520ed7bd0e3856b8cca7051f2ee90ab..1dec8f9d04b461299dcd7422c43d5dd3c4b11c5c 100644 (file)
--- a/test/CodeGen/ARM/select-imm.ll
+++ b/test/CodeGen/ARM/select-imm.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=arm                | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2
+; RUN: llc < %s -march=arm                  | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s --check-prefix=T2
 
 define i32 @t1(i32 %c) nounwind readnone {
 entry:
@@ -25,7 +25,7 @@ entry:
 ; ARM: movle r0, #123
 
 ; T2: t2:
-; T2: mov r0, #123
+; T2: mov.w r0, #123
 ; T2: movwgt r0, #357
 
   %0 = icmp sgt i32 %c, 1
@@ -40,9 +40,22 @@ entry:
 ; ARM: moveq r0, #1
 
 ; T2: t3:
-; T2: mov r0, #0
+; T2: mov.w r0, #0
 ; T2: moveq r0, #1
   %0 = icmp eq i32 %a, 160
   %1 = zext i1 %0 to i32
   ret i32 %1
 }
+
+define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
+entry:
+; ARM: t4:
+; ARM: ldr
+; ARM: movlt
+
+; T2: t4:
+; T2: mvnlt.w r0, #11141290
+  %0 = icmp slt i32 %a, %b
+  %1 = select i1 %0, i32 4283826005, i32 %x
+  ret i32 %1
+}