Bug fix: unconditional branch should break the single dmb effect for adjacent stores

diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 202b19525e1a0f50afb035c8c8afbcbcf5006986..b783b15d988045b5373693fc5ee253ac73165999 100644 (file)
--- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1597,6 +1597,30 @@ static bool isLoad(MachineInstr* MI) {
   }
 }
 
+static bool isBranch(MachineInstr* MI) {
+  switch (MI->getOpcode()) {
+    default: { return false; }
+    case AArch64::B:
+    case AArch64::BR:
+    case AArch64::Bcc:
+    case AArch64::CBZW:
+    case AArch64::CBZX:
+    case AArch64::CBNZW:
+    case AArch64::CBNZX:
+    case AArch64::TBZW:
+    case AArch64::TBZX:
+    case AArch64::TBNZW:
+    case AArch64::TBNZX:
+    case AArch64::BLR:
+    case AArch64::BL:
+//    case AArch64::BX:
+//    case AArch64::BLX:
+    {
+      return true;
+    }
+  }
+}
+
 bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
                                         bool enableNarrowLdOpt) {
   // XXX-update: Try to add a 'dmb ld' fence before a relaxed store in the form
@@ -1666,7 +1690,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
         DEBUG(dbgs() << "Added barrier instruction\n\t" << *DMBInst
                      << "\n\tfor " << *MI << "\n");
         // Skip all the way till we reach the end of the basic block or a load.
-        while (MBBI != E && !isLoad(&*MBBI)) {
+        while (MBBI != E && !isLoad(&*MBBI) && !isBranch(MBBI)) {
           MBBI++;
         }
         break;