[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.

Differential Revision: http://reviews.llvm.org/D5800

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222352 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td
index a1067787934991c9fa76432d29718680e79a00b2..4a4cca9ba1bbebdd744bd205e710894ce16ac340 100644 (file)
--- a/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -31,6 +31,10 @@ def uimm4_andi : Operand<i32> {
   let EncoderMethod = "getUImm4AndValue";
 }
 
+def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
+                                           ((Imm % 4 == 0) &&
+                                            Imm < 28 && Imm > 0);}]>;
+
 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
 
 def immZExtAndi16 : ImmLeaf<i32,
@@ -528,6 +532,8 @@ let Predicates = [InMicroMips] in {
 // MicroMips arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
+def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
+              (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
               (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
 def : MipsPat<(add GPR32:$src, immSExt16:$imm),

diff --git a/test/CodeGen/Mips/micromips-addiu.ll b/test/CodeGen/Mips/micromips-addiu.ll
index 4a87efe6447774d3475df0b82596279f74e7d1fe..c5bee34028c8721542b90d125f6e61ee42275f1c 100644 (file)
--- a/test/CodeGen/Mips/micromips-addiu.ll
+++ b/test/CodeGen/Mips/micromips-addiu.ll
@@ -3,6 +3,7 @@
 
 @x = global i32 65504, align 4
 @y = global i32 60929, align 4
+@z = global i32 60929, align 4
 @.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
 
 define i32 @main() nounwind {
@@ -16,6 +17,11 @@ entry:
   %addiu2 = add i32 %1, 55
   %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
                                   ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu2)
+
+  %2 = load i32* @z, align 4
+  %addiu3 = add i32 %2, 24
+  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
+                                  ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu3)
   ret i32 0
 }
 
@@ -23,3 +29,4 @@ declare i32 @printf(i8*, ...)
 
 ; CHECK: addius5  ${{[0-9]+}}, -7
 ; CHECK: addiu    ${{[0-9]+}}, ${{[0-9]+}}, 55
+; CHECK: addiur2  ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, 24