case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
- case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
case XCoreISD::STWSP : return "XCoreISD::STWSP";
case XCoreISD::RETSP : return "XCoreISD::RETSP";
case XCoreISD::LADD : return "XCoreISD::LADD";
}
}
-/// LowerCallResult - Lower the result values of a call into the
-/// appropriate copies out of appropriate physical registers / memory locations.
-static SDValue
-LowerCallResult(SDValue Chain, SDValue InFlag,
- const SmallVectorImpl<CCValAssign> &RVLocs,
- SDLoc dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) {
- SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
- // Copy results out of physical registers.
- for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
- const CCValAssign &VA = RVLocs[i];
- if (VA.isRegLoc()) {
- Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
- InFlag).getValue(1);
- InFlag = Chain.getValue(2);
- InVals.push_back(Chain.getValue(0));
- } else {
- assert(VA.isMemLoc());
- ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
- InVals.size()));
- // Reserve space for this result.
- InVals.push_back(SDValue());
- }
- }
-
- // Copy results out of memory.
- SmallVector<SDValue, 4> MemOpChains;
- for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
- int offset = ResultMemLocs[i].first;
- unsigned index = ResultMemLocs[i].second;
- SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
- SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
- SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops, 2);
- InVals[index] = load;
- MemOpChains.push_back(load.getValue(1));
- }
-
- // Transform all loads nodes into one single node because
- // all load nodes are independent of each other.
- if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
- &MemOpChains[0], MemOpChains.size());
-
- return Chain;
-}
-
/// LowerCCCCallTo - functions arguments are copied from virtual
/// regs to (physical regs)/(stack frame), CALLSEQ_START and
/// CALLSEQ_END are emitted.
CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
- SmallVector<CCValAssign, 16> RVLocs;
- // Analyze return values to determine the number of bytes of stack required.
- CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
- getTargetMachine(), RVLocs, *DAG.getContext());
- RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
- RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
-
// Get a count of how many bytes are to be pushed on the stack.
- unsigned NumBytes = RetCCInfo.getNextStackOffset();
+ unsigned NumBytes = CCInfo.getNextStackOffset();
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy(), true), dl);
// Handle result values, copying them out of physregs into vregs that we
// return.
- return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
+ return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
+ Ins, dl, DAG, InVals);
+}
+
+/// LowerCallResult - Lower the result values of a call into the
+/// appropriate copies out of appropriate physical registers.
+SDValue
+XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ SDLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const {
+
+ // Assign locations to each value returned by this call.
+ SmallVector<CCValAssign, 16> RVLocs;
+ CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+ getTargetMachine(), RVLocs, *DAG.getContext());
+
+ CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
+
+ // Copy all of the result registers out of their specified physreg.
+ for (unsigned i = 0; i != RVLocs.size(); ++i) {
+ Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
+ RVLocs[i].getValVT(), InFlag).getValue(1);
+ InFlag = Chain.getValue(2);
+ InVals.push_back(Chain.getValue(0));
+ }
+
+ return Chain;
}
//===----------------------------------------------------------------------===//
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
unsigned LRSaveSize = StackSlotSize;
- if (!isVarArg)
- XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
-
// All getCopyFromReg ops must precede any getMemcpys to prevent the
// scheduler clobbering a register before it has been copied.
// The stages are:
LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
- if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
- return false;
- if (CCInfo.getNextStackOffset() != 0 && isVarArg)
- return false;
- return true;
+ return CCInfo.CheckReturn(Outs, RetCC_XCore);
}
SDValue
const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const {
- XCoreFunctionInfo *XFI =
- DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
- MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
-
// CCValAssign - represent the assignment of
// the return value to a location
SmallVector<CCValAssign, 16> RVLocs;
getTargetMachine(), RVLocs, *DAG.getContext());
// Analyze return values.
- if (!isVarArg)
- CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4);
-
CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
SDValue Flag;
// Return on XCore is always a "retsp 0"
RetOps.push_back(DAG.getConstant(0, MVT::i32));
- SmallVector<SDValue, 4> MemOpChains;
- // Handle return values that must be copied to memory.
- for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
+ // Copy the result values into the output registers.
+ for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
- if (VA.isRegLoc())
- continue;
- assert(VA.isMemLoc());
- if (isVarArg) {
- report_fatal_error("Can't return value from vararg function in memory");
- }
+ assert(VA.isRegLoc() && "Can only return in registers!");
- int Offset = VA.getLocMemOffset();
- unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
- // Create the frame index object for the memory location.
- int FI = MFI->CreateFixedObject(ObjSize, Offset, false);
-
- // Create a SelectionDAG node corresponding to a store
- // to this memory location.
- SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
- MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN,
- MachinePointerInfo::getFixedStack(FI), false, false,
- 0));
- }
-
- // Transform all store nodes into one single node because
- // all stores are independent of each other.
- if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
- &MemOpChains[0], MemOpChains.size());
-
- // Now handle return values copied to registers.
- for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
- CCValAssign &VA = RVLocs[i];
- if (!VA.isRegLoc())
- continue;
- // Copy the result values into the output registers.
- Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ OutVals[i], Flag);
// guarantee that all emitted copies are
// stuck together, avoiding something bad
%0 = type { i32, i32, i32, i32 }
%1 = type { i32, i32, i32, i32, i32 }
-; Structs of 4 words are returned in registers
-define internal %0 @ReturnBigStruct() nounwind readnone {
+; Structs of 4 words can be returned in registers
+define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
entry:
%0 = insertvalue %0 zeroinitializer, i32 12, 0
%1 = insertvalue %0 %0, i32 24, 1
; CHECK: ldc r3, 24601
; CHECK: retsp 0
-; Structs of more than 4 words are partially returned in memory so long as the
-; function is not variadic.
-define { i32, i32, i32, i32, i32} @f(i32, i32, i32, i32, i32) nounwind readnone {
-; CHECK-LABEL: f:
-; CHECK: ldc [[REGISTER:r[0-9]+]], 5
-; CHECK-NEXT: stw [[REGISTER]], sp[2]
-; CHECK-NEXT: retsp 0
-body:
- ret { i32, i32, i32, i32, i32} { i32 undef, i32 undef, i32 undef, i32 undef, i32 5}
-}
-
-@x = external global i32
-@y = external global i32
-
-; Check we call a function returning more than 4 words correctly.
-define i32 @g() nounwind {
-; CHECK-LABEL: g:
-; CHECK: entsp 3
-; CHECK: ldc [[REGISTER:r[0-9]+]], 0
-; CHECK: stw [[REGISTER]], sp[1]
-; CHECK: bl f
-; CHECK-NEXT: ldw r0, sp[2]
-; CHECK-NEXT: retsp 3
-;
-body:
- %0 = call { i32, i32, i32, i32, i32 } @f(i32 0, i32 0, i32 0, i32 0, i32 0)
- %1 = extractvalue { i32, i32, i32, i32, i32 } %0, 4
- ret i32 %1
-}
-
-; Variadic functions return structs bigger than 4 words via a hidden
-; sret-parameter
-define internal %1 @ReturnBigStruct2(i32 %dummy, ...) nounwind readnone {
+; Structs bigger than 4 words are returned via a hidden hidden sret-parameter
+define internal fastcc %1 @ReturnBigStruct2() nounwind readnone {
entry:
%0 = insertvalue %1 zeroinitializer, i32 12, 0
%1 = insertvalue %1 %0, i32 24, 1
projects / oota-llvm.git / commitdiff