spell this right

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23099 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 01ee17ef7cb48eb4de69d30aebf2d5e3c928f471..fc79f592047fd07bf79211a3626d1087ea7c0c44 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -143,7 +143,7 @@ class Instruction {
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
-  bit usesCustomDAGSChedInserter = 0; // Pseudo instr needing special help.
+  bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
 }
 
 

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index b3bb46db992362c197bced426a471bdb9f13bac5..bd02ccdcef02488698cc1ecb2c7dcd157428e964 100644 (file)
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -250,7 +250,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   isCommutable = R->getValueAsBit("isCommutable");
   isTerminator = R->getValueAsBit("isTerminator");
   hasDelaySlot = R->getValueAsBit("hasDelaySlot");
-  usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSChedInserter");
+  usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
   hasVariableNumberOfOperands = false;
   
   try {