rk3036&rk312x:clk:modify gpu clk name for dvfs

diff --git a/arch/arm/boot/dts/rk3036-clocks.dtsi b/arch/arm/boot/dts/rk3036-clocks.dtsi
index 9b60bf8d65670e0365eae38ab1222c27c4e494de..81691f1a83ea52f4e0c8739f2e4065f7e9be6a92 100755 (executable)
--- a/arch/arm/boot/dts/rk3036-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3036-clocks.dtsi
@@ -1109,11 +1109,11 @@
                                        #address-cells = <1>;
                                        #size-cells = <1>;
 
-                                       clk_gpu_pre_div: clk_gpu_pre_div {
+                                       clk_gpu_div: clk_gpu_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <0 5>;
-                                               clocks = <&clk_gpu_pre>;
-                                               clock-output-names = "clk_gpu_pre";
+                                               clocks = <&clk_gpu>;
+                                               clock-output-names = "clk_gpu";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
@@ -1123,11 +1123,11 @@
 
                                        /* reg[7:5]: reserved */
 
-                                       clk_gpu_pre: clk_gpu_pre_mux {
+                                       clk_gpu: clk_gpu_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <8 2>;
                                                clocks = <&dummy>, <&dummy>, <&clk_gpll>;
-                                               clock-output-names = "clk_gpu_pre";
+                                               clock-output-names = "clk_gpu";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
                                        };
@@ -1258,7 +1258,7 @@
                                                <&pclk_cpu_pre>,                <&dummy>,
                                                <&dummy>,               <&aclk_vcodec_pre>,
 
-                                               <&aclk_vcodec_pre>,             <&clk_gpu_pre>,
+                                               <&aclk_vcodec_pre>,             <&clk_gpu>,
                                                <&hclk_peri_pre>,               <&dummy>;
 
                                        clock-output-names =
@@ -1271,7 +1271,7 @@
                                                "g_pclk_hdmi",          "reserved",
                                                "reserved",             "aclk_vcodec_pre",
 
-                                               "hclk_vcodec",          "clk_gpu_pre",
+                                               "hclk_vcodec",          "clk_gpu",
                                                "g_hclk_sfc",           "reserved";
                                        rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
 

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
old mode 100644 (file)
new mode 100755 (executable)
index e0bb7c3..d845b1a
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -254,7 +254,7 @@
                        <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
                        <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
                        <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
-                       <&clk_gpu_pre 300000000>,        <&aclk_vio_pre 300000000>,
+                       <&clk_gpu 300000000>,    <&aclk_vio_pre 300000000>,
                        <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
                        <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
                        <&clk_mac_ref_div 25000000>;
@@ -320,7 +320,7 @@
                                <&clk_gates1 13>,
                                <&clk_gates8 2>,/*pclk_uart2*/
 
-                               <&clk_gpu_pre>,
+                               <&clk_gpu>,
 
                                /*jtag*/
                                <&clk_gates1 3>;/*clk_jtag*/

diff --git a/arch/arm/boot/dts/rk312x-clocks.dtsi b/arch/arm/boot/dts/rk312x-clocks.dtsi
index d1b1ab073ec0163f61b1a42fc7a8569bdc3006f6..e7b95493a7329959ae9656e19a717e454879548a 100755 (executable)
--- a/arch/arm/boot/dts/rk312x-clocks.dtsi
+++ b/arch/arm/boot/dts/rk312x-clocks.dtsi
@@ -1470,11 +1470,11 @@
                                        #address-cells = <1>;
                                        #size-cells = <1>;
 
-                                       clk_gpu_pre_div: clk_gpu_pre_div {
+                                       clk_gpu_div: clk_gpu_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <0 5>;
-                                               clocks = <&clk_gpu_pre>;
-                                               clock-output-names = "clk_gpu_pre";
+                                               clocks = <&clk_gpu>;
+                                               clock-output-names = "clk_gpu";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
@@ -1482,11 +1482,11 @@
                                                rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
                                        };
 
-                                       clk_gpu_pre: clk_gpu_pre_mux {
+                                       clk_gpu: clk_gpu_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <5 3>;
                                                clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
-                                               clock-output-names = "clk_gpu_pre";
+                                               clock-output-names = "clk_gpu";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
                                        };
@@ -1635,7 +1635,7 @@
                                                <&pclk_cpu_pre>,                <&clk_vepu>,
                                                <&clk_hevc_core>,               <&clk_vdpu>,
 
-                                               <&hclk_vdpu>,           <&clk_gpu_pre>,
+                                               <&hclk_vdpu>,           <&clk_gpu>,
                                                <&aclk_peri>,           <&clk_sfc>;
 
                                        clock-output-names =
@@ -1648,7 +1648,7 @@
                                                "g_pclk_hdmi",          "clk_vepu",
                                                "clk_hevc_core",                "clk_vdpu",
 
-                                               "hclk_vdpu",            "clk_gpu_pre",
+                                               "hclk_vdpu",            "clk_gpu",
                                                "g_hclk_gps",           "clk_sfc";
                                        rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
 

diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index 9bbb421f3088e417ac1ec072afdf4d44883d269e..4835f0f6df6b2a3a345c41444ae3bafcef4df50f 100755 (executable)
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -205,7 +205,7 @@
                        <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
                        <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
                        <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
-                       <&sclk_lcdc0 &clk_cpll>, <&clk_gpu_pre &clk_gpll_div2>,
+                       <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
                        <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
                        <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
                        <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
@@ -216,7 +216,7 @@
                        <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
                        <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
                        <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
-                       <&pclk_peri_pre 75000000>, <&clk_gpu_pre 300000000>,
+                       <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
                        <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
                        <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
                        <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
@@ -323,7 +323,7 @@
                                <&clk_gates1 13>,
                                <&clk_gates8 2>,/*pclk_uart2*/
 
-                               <&clk_gpu_pre>,
+                               <&clk_gpu>,
 
                                /*jtag*/
                                <&clk_gates1 3>,/*clk_jtag*/