Make sure SEXTLOAD of the specific type is supported on the target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index df951a51bb2d191402e75d35b6240f831a7350a0..569b1a91d7117fd77795b11a9e1047b95fd5771e 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2272,9 +2272,13 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
   MVT::ValueType VT = N->getValueType(0);
   MVT::ValueType EVT = N->getValueType(0);
 
+  // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
+  // extended to VT.
   if (Opc == ISD::SIGN_EXTEND_INREG) {
     ExtType = ISD::SEXTLOAD;
     EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+    if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
+      return SDOperand();
   }
 
   unsigned EVTBits = MVT::getSizeInBits(EVT);