drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY
authorHai Li <hali@codeaurora.org>
Fri, 11 Sep 2015 19:56:09 +0000 (15:56 -0400)
committerRob Clark <robdclark@gmail.com>
Thu, 22 Oct 2015 19:39:54 +0000 (15:39 -0400)
The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

index f1a7c7b46420985e7f2c63937e08963717056b81..edf74110ced7bd1ec15a96f96114681006b6cb43 100644 (file)
@@ -99,16 +99,14 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
                dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);
                dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);
                dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);
+               dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0);
                dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);
                dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);
                dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);
                dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);
        }
-       dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0);
-       dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5);
-       dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa);
-       dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf);
 
+       dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0);
        dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);
        dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);
        dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);