ARM: rockchip: rk3036 add cpu axi bus support

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 7c5f838cbcf2788d2ad0c210a7d873c21b29ebf7..837e54efc32010ccf7cb881e859e71895ab690d0 100755 (executable)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -50,6 +50,51 @@
                             <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
        };
 
+       cpu_axi_bus: cpu_axi_bus {
+               compatible = "rockchip,cpu_axi_bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               qos {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       core {
+                               reg = <0x1012a000 0x20>;
+                               rockchip,priority = <3 2>;
+                       };
+                       peri {
+                               reg = <0x1012c000 0x20>;
+                       };
+                       gpu {
+                               reg = <0x1012d000 0x20>;
+                       };
+                       vpu {
+                               reg = <0x1012e000 0x20>;
+                       };
+                       hevc {
+                               reg = <0x1012e080 0x20>;
+                       };
+                       vio {
+                               reg = <0x1012f000 0x20>;
+                               rockchip,priority = <3 3>;
+                       };
+               };
+
+               msch {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       msch@10128000 {
+                               reg = <0x10128000 0x40>;
+                               rockchip,read-latency = <0x80>;
+                       };
+               };
+       };
+
        sram: sram@10080000 {
                compatible = "mmio-sram";
                reg = <0x10080000 0x2000>;

diff --git a/arch/arm/mach-rockchip/cpu_axi.h b/arch/arm/mach-rockchip/cpu_axi.h
index 4c346dec79f26d42f461960aa0399a3431ca89bf..53a94f108285a9f3a865870cad3ccc147a175e9d 100644 (file)
--- a/arch/arm/mach-rockchip/cpu_axi.h
+++ b/arch/arm/mach-rockchip/cpu_axi.h
@@ -12,7 +12,8 @@
 #define CPU_AXI_QOS_MODE_LIMITER        2
 #define CPU_AXI_QOS_MODE_REGULATOR      3
 
-#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l)        ((((h) & 3) << 2) | ((l) & 3))
+#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
+       ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
 #define CPU_AXI_SET_QOS_PRIORITY(h, l, base) \
        writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), base + CPU_AXI_QOS_PRIORITY)