Eliminate usage of MRegisterInfo::getRegClass(physreg)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17240 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.cpp b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
index 9375c2c5105c5f58e3f439c04ecc015c5cc84a16..0ff039438c75077637a9617ad326b94a891ade80 100644 (file)
--- a/lib/Target/PowerPC/PPC64RegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
@@ -48,6 +48,13 @@ PPC64RegisterInfo::PPC64RegisterInfo()
   ImmToIdxMap[PPC::ADDI] = PPC::ADD;
 }
 
+static const TargetRegisterClass *getClass(unsigned SrcReg) {
+  if (PPC64::FPRCRegisterClass->contains(SrcReg))
+       return PPC64::FPRCRegisterClass;
+  assert(PPC64::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
+  return PPC64::GPRCRegisterClass;
+}
+
 static unsigned getIdx(const TargetRegisterClass *RC) {
   if (RC == PPC64::GPRCRegisterClass) {
     switch (RC->getSize()) {
@@ -75,8 +82,7 @@ PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   static const unsigned Opcode[] = { 
     PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD 
   };
-  const TargetRegisterClass *RC = getRegClass(SrcReg);
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(SrcReg))];
   if (SrcReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
@@ -94,8 +100,7 @@ PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   static const unsigned Opcode[] = { 
     PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD 
   };
-  const TargetRegisterClass *RC = getRegClass(DestReg);
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(DestReg))];
   if (DestReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
     addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index a7b5cb5badf0ff5df7dd2dda323cf212804ed145..3660c2f476682fb3f20b384dff2fd4ba4446460f 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -48,6 +48,13 @@ PPC32RegisterInfo::PPC32RegisterInfo()
   ImmToIdxMap[PPC::ADDI] = PPC::ADD;
 }
 
+static const TargetRegisterClass *getClass(unsigned SrcReg) {
+  if (PPC32::FPRCRegisterClass->contains(SrcReg))
+       return PPC32::FPRCRegisterClass;
+  assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
+  return PPC32::GPRCRegisterClass;
+}
+
 static unsigned getIdx(const TargetRegisterClass *RC) {
   if (RC == PPC32::GPRCRegisterClass) {
     switch (RC->getSize()) {
@@ -71,12 +78,10 @@ void
 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx) const {
-  const TargetRegisterClass *RC = getRegClass(SrcReg);
   static const unsigned Opcode[] = { 
     PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD 
   };
-
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(SrcReg))];
   if (SrcReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
@@ -94,8 +99,7 @@ PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   static const unsigned Opcode[] = { 
     PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD 
   };
-  const TargetRegisterClass *RC = getRegClass(DestReg);
-  unsigned OC = Opcode[getIdx(RC)];
+  unsigned OC = Opcode[getIdx(getClass(DestReg))];
   if (DestReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
     addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);