Add memory operand and int regs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28896 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 634aa01bc92a12d97ef508a536ae54219db6dcea..1c1c39a57ecc10439d67a42c0ae7dba155783bec 100644 (file)
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -62,6 +62,10 @@ namespace {
 
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode);
+    bool PrintAsmMemoryOperand(const MachineInstr *MI, 
+                              unsigned OpNo,
+                              unsigned AsmVariant, 
+                              const char *ExtraCode);
   };
 } // end of anonymous namespace
 
@@ -277,3 +281,13 @@ bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
   printOperand(MI, OpNo);
   return false;
 }
+
+bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 
+                                           unsigned OpNo,
+                                           unsigned AsmVariant, 
+                                           const char *ExtraCode) {
+  if (ExtraCode && ExtraCode[0])
+    return true; // Unknown modifier.
+  printOperand(MI, OpNo);
+  return false;
+}

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index bbb18cb2c058a9a8bc83f8063150c61fe89698de..7443371be3a9d262d1a59f325e451d24f8e54fa7 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -119,6 +119,24 @@ namespace {
       return "Alpha DAG->DAG Pattern Instruction Selection";
     } 
 
+    /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+    /// inline asm expressions.
+    virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+                                              char ConstraintCode,
+                                              std::vector<SDOperand> &OutOps,
+                                              SelectionDAG &DAG) {
+      SDOperand Op0;
+      switch (ConstraintCode) {
+      default: return true;
+      case 'm':   // memory
+       Select(Op0, Op);
+        break;
+      }
+      
+      OutOps.push_back(Op0);
+      return false;
+    }
+    
 // Include the pieces autogenerated from the target description.
 #include "AlphaGenDAGISel.inc"
     

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index b18ee865577a36c25ae26019e08d7f5484ea6240..3f21616778c8e9e45b1ffddbc0a1877aea9ab71b 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -591,6 +591,7 @@ AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
   switch (ConstraintLetter) {
   default: break;
   case 'f':
+  case 'r':
     return C_RegisterClass;
   }  
   return TargetLowering::getConstraintType(ConstraintLetter);
@@ -614,6 +615,19 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                    Alpha::F24, Alpha::F25, Alpha::F26, 
                                   Alpha::F27, Alpha::F28, Alpha::F29, 
                                   Alpha::F30, Alpha::F31, 0);
+    case 'r': 
+      return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 , 
+                                  Alpha::R3 , Alpha::R4 , Alpha::R5 , 
+                                  Alpha::R6 , Alpha::R7 , Alpha::R8 , 
+                                  Alpha::R9 , Alpha::R10, Alpha::R11, 
+                                   Alpha::R12, Alpha::R13, Alpha::R14, 
+                                  Alpha::R15, Alpha::R16, Alpha::R17, 
+                                  Alpha::R18, Alpha::R19, Alpha::R20, 
+                                  Alpha::R21, Alpha::R22, Alpha::R23, 
+                                   Alpha::R24, Alpha::R25, Alpha::R26, 
+                                  Alpha::R27, Alpha::R28, Alpha::R29, 
+                                  Alpha::R30, Alpha::R31, 0);
+ 
     }
   }