clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi

sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock.
The patch models this dependency using parent/child hirerarchy.

The patch fixes issue with system hangs during mixer device access, mixer uses
sclk_hdmiphy descendant clock.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 940f02837b824869932d3e6b63462942577a708c..88e8c6bbd77ff8ea6919bc6c1ef7bd3fdc1324ae 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -505,7 +505,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
 /* fixed rate clocks generated inside the soc */
 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
        FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
-       FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+       FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
        FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
 };