MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
- bool isMips64() const {
- return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
+ bool isGP64() const {
+ return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
}
bool isFP64() const {
const MCExpr *ExprOffset;
unsigned TmpRegNum;
unsigned AtRegNum = getReg(
- (isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
+ (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
// 1st operand is either the source or destination register.
assert(Inst.getOperand(0).isReg() && "expected register operand kind");
unsigned RegOpNum = Inst.getOperand(0).getReg();
}
unsigned MipsAsmParser::getGPR(int RegNo) {
- return getReg((isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
- RegNo);
+ return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
+ RegNo);
}
-
int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
if (RegNum >
getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
SMLoc S = Parser.getTok().getLoc();
Parser.Lex(); // Eat dollar token.
// Parse the register operand.
- if (!tryParseRegisterOperand(Operands, isMips64())) {
+ if (!tryParseRegisterOperand(Operands, isGP64())) {
if (getLexer().is(AsmToken::LParen)) {
// Check if it is indexed addressing operand.
Operands.push_back(MipsOperand::CreateToken("(", S));
return true;
Parser.Lex(); // Eat the dollar
- if (tryParseRegisterOperand(Operands, isMips64()))
+ if (tryParseRegisterOperand(Operands, isGP64()))
return true;
if (!getLexer().is(AsmToken::RParen))
bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
StartLoc = Parser.getTok().getLoc();
- RegNo = tryParseRegister(isMips64());
+ RegNo = tryParseRegister(isGP64());
EndLoc = Parser.getTok().getLoc();
return (RegNo == (unsigned)-1);
}
// Zero register assumed, add a memory operand with ZERO as its base.
Operands.push_back(MipsOperand::CreateMem(
- isMips64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
+ isGP64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
return MatchOperand_Success;
}
Error(Parser.getTok().getLoc(), "'(' expected");
Parser.Lex(); // Eat the '(' token.
}
- Res = parseRegs(Operands, isMips64() ? (int)MipsOperand::Kind_GPR64
- : (int)MipsOperand::Kind_GPR32);
+ Res = parseRegs(Operands, isGP64() ? (int)MipsOperand::Kind_GPR64
+ : (int)MipsOperand::Kind_GPR32);
if (Res != MatchOperand_Success)
return Res;
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
- if (!isMips64())
+ if (!isGP64())
return MatchOperand_NoMatch;
return parseRegs(Operands, (int)MipsOperand::Kind_GPR64);
}
APInt IntVal(32, -1);
if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
- isMips64() ? Mips::GPR64RegClassID
- : Mips::GPR32RegClassID);
+ isGP64() ? Mips::GPR64RegClassID
+ : Mips::GPR32RegClassID);
else {
// Lookup for the register with the corresponding name.
switch (Kind) {
((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
// Check if Architecture and ABI are compatible.
- assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) ||
- (hasMips64() && (isABI_N32() || isABI_N64()))) &&
+ assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
+ (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
"Invalid Arch & ABI pair.");
if (hasMSA() && !isFP64bit())
RegClassVector &CriticalPathRCs) const {
Mode = TargetSubtargetInfo::ANTIDEP_NONE;
CriticalPathRCs.clear();
- CriticalPathRCs.push_back(hasMips64() ?
- &Mips::GPR64RegClass : &Mips::GPR32RegClass);
+ CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
+ : &Mips::GPR32RegClass);
return OptLevel >= CodeGenOpt::Aggressive;
}