[mips][msa] Separate the configuration of int/float vector types since they will...

No functional change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190506 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index 2436e540f143aa7dc194cfbc7821065837be34de..5999e197f36778dc3a615a2bbaf070a36b5f9bf5 100644 (file)
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -83,13 +83,13 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
     setOperationAction(ISD::MUL, MVT::v2i16, Legal);
 
   if (Subtarget->hasMSA()) {
-    addMSAType(MVT::v16i8, &Mips::MSA128BRegClass);
-    addMSAType(MVT::v8i16, &Mips::MSA128HRegClass);
-    addMSAType(MVT::v4i32, &Mips::MSA128WRegClass);
-    addMSAType(MVT::v2i64, &Mips::MSA128DRegClass);
-    addMSAType(MVT::v8f16, &Mips::MSA128HRegClass);
-    addMSAType(MVT::v4f32, &Mips::MSA128WRegClass);
-    addMSAType(MVT::v2f64, &Mips::MSA128DRegClass);
+    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
+    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
+    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
+    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
+    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
+    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
+    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
   }
 
   if (!Subtarget->mipsSEUsesSoftFloat()) {
@@ -148,7 +148,21 @@ llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
 }
 
 void MipsSETargetLowering::
-addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
+addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
+  addRegisterClass(Ty, RC);
+
+  // Expand all builtin opcodes.
+  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+    setOperationAction(Opc, Ty, Expand);
+
+  setOperationAction(ISD::BITCAST, Ty, Legal);
+  setOperationAction(ISD::LOAD, Ty, Legal);
+  setOperationAction(ISD::STORE, Ty, Legal);
+
+}
+
+void MipsSETargetLowering::
+addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
   addRegisterClass(Ty, RC);
 
   // Expand all builtin opcodes.

diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h
index dde0c23c35d9cf37f2f753d1de8292593fe3b92f..016d4adbf73adc9a9a799df35ebdca31f7e7f44a 100644 (file)
--- a/lib/Target/Mips/MipsSEISelLowering.h
+++ b/lib/Target/Mips/MipsSEISelLowering.h
@@ -22,7 +22,9 @@ namespace llvm {
   public:
     explicit MipsSETargetLowering(MipsTargetMachine &TM);
 
-    void addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
+    void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
+    void addMSAFloatType(MVT::SimpleValueType Ty,
+                         const TargetRegisterClass *RC);
 
     virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;