oops
authorAndrew Lenharth <andrewl@lenharth.org>
Wed, 2 Feb 2005 17:01:31 +0000 (17:01 +0000)
committerAndrew Lenharth <andrewl@lenharth.org>
Wed, 2 Feb 2005 17:01:31 +0000 (17:01 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20003 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaRegisterInfo.td

index 416500293780881f697089a9bb2b616fa7ac1ed7..fd965de0bf42f3e312fe9bfe1c9de68ac396beb9 100644 (file)
@@ -81,7 +81,7 @@ def GPRC : RegisterClass<i64, 64,
 //Volitle
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27,
 //Non-Volitile
-     R9, R10, R11, R12, R13, R14, R15, R26, /*R28,*/ R29, /* R30, R31*/ ]>;
+     R9, R10, R11, R12, R13, R14, R15, R26, /* R28, */ R29 /* R30, R31*/ ]>;
 //R28 is reserved for the assembler
 
 //Don't allocate 15, 29, 30, 31