[mips] Implement tlbp, tlbr, tlbwi, and tlbwr

Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208301 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index 4afc327f7f20769b33b45312a533abcddfb9f13c..0377eabed78d5c2b937012a1ea495b31804550ff 100644 (file)
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -843,3 +843,12 @@ class BARRIER_FM<bits<5> op> : StdArch {
   let Inst{10-6} = op; // Operation
   let Inst{5-0} = 0;   // SLL
 }
+
+class COP0_TLB_FM<bits<6> op> : StdArch {
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x10; // COP0
+  let Inst{25} = 1;       // CO
+  let Inst{24-6} = 0;
+  let Inst{5-0} = op;     // Operation
+}

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 4c3e2e39d5f06c04093055a8ea0096859e52caec..d9d137b0030cd0926b5237a4e9f9b6e241ff7d58 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1207,6 +1207,13 @@ def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
 
+class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
+                                      FrmOther>;
+def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
+def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
+def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
+def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/Mips/mips1/valid-xfail.s b/test/MC/Mips/mips1/valid-xfail.s
index 784338cc3716853af385cc48b835a85ee545b5ef..a970a91ecc8868a751320550a77af914df1e847f 100644 (file)
--- a/test/MC/Mips/mips1/valid-xfail.s
+++ b/test/MC/Mips/mips1/valid-xfail.s
@@ -7,10 +7,6 @@
 # XFAIL: *
 
        .set noat
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr
        lwc0    c0_entrylo,-7321($s2)
        lwc3    $10,-32265($k0)
        swc0    c0_prid,18904($s3)

diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s
index 4ad74acb537e857d2ef78c16bb936410af920ba9..9d619697cb28c07c2806b97b29bc0b7e88927dd4 100644 (file)
--- a/test/MC/Mips/mips1/valid.s
+++ b/test/MC/Mips/mips1/valid.s
@@ -92,4 +92,8 @@
        swc2    $25,24880($s0)
        swl     $t7,13694($s3)
        swr     $s1,-26590($t6)
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        xor     $s2,$a0,$s8

diff --git a/test/MC/Mips/mips2/valid-xfail.s b/test/MC/Mips/mips2/valid-xfail.s
index e8b8666da6eb952ea1949c01fa0c2a188868d082..9c175b10ccecd6c1dfe0fb741b8e05300dab0589 100644 (file)
--- a/test/MC/Mips/mips2/valid-xfail.s
+++ b/test/MC/Mips/mips2/valid-xfail.s
@@ -10,7 +10,3 @@
        ldc3    $29,-28645($s1)
        lwc3    $10,-32265($k0)
        sdc3    $12,5835($t2)
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr

diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s
index dc4a8b6ea91822fccce8f67b56e86e82edfccfd1..8e2331f4e3508eeb8966fa8031322dbd854118b3 100644 (file)
--- a/test/MC/Mips/mips2/valid.s
+++ b/test/MC/Mips/mips2/valid.s
@@ -109,6 +109,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647

diff --git a/test/MC/Mips/mips3/valid-xfail.s b/test/MC/Mips/mips3/valid-xfail.s
index 329dde12a249f21fb8fc9bfc8de995e9725aff69..c3905715065ed488d8d03b42cb135b6ee45f51c4 100644 (file)
--- a/test/MC/Mips/mips3/valid-xfail.s
+++ b/test/MC/Mips/mips3/valid-xfail.s
@@ -8,7 +8,3 @@
 
        .set noat
        lwc3    $10,-32265($k0)
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr

diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s
index 68f97038d4a8927dc39a5809d3463ab9054baefb..d7bae7df2a4a8f9057aeec6fac45982f4abc737c 100644 (file)
--- a/test/MC/Mips/mips3/valid.s
+++ b/test/MC/Mips/mips3/valid.s
@@ -159,6 +159,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647

diff --git a/test/MC/Mips/mips32/valid-xfail.s b/test/MC/Mips/mips32/valid-xfail.s
index 65cebd381856aa2f52fc17df0eb2db1f791ebb52..15a4eecee52569ed1ed73d16ee3f315a016815a7 100644 (file)
--- a/test/MC/Mips/mips32/valid-xfail.s
+++ b/test/MC/Mips/mips32/valid-xfail.s
@@ -38,7 +38,3 @@
        ldc3    $29,-28645($s1)
        rorv    $t5,$a3,$s5
        sdc3    $12,5835($t2)
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr

diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s
index 2abdd780b33c90a8643e479e4e3f3db248781803..be31475a9cbd3fa89a77f55493abd77aa332c93f 100644 (file)
--- a/test/MC/Mips/mips32/valid.s
+++ b/test/MC/Mips/mips32/valid.s
@@ -134,6 +134,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647

diff --git a/test/MC/Mips/mips32r2/valid-xfail.s b/test/MC/Mips/mips32r2/valid-xfail.s
index 623c7f6cb477fa06820bbb5faecb4f94ff61af73..b044e7b8edce1382570722816d80d7f3bdf7ef12 100644 (file)
--- a/test/MC/Mips/mips32r2/valid-xfail.s
+++ b/test/MC/Mips/mips32r2/valid-xfail.s
@@ -304,10 +304,6 @@
        tlbgwr
        tlbinv
        tlbinvf
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr
        trunc.l.d       $f23,$f23
        trunc.l.s       $f28,$f31
        wrpgpr  $zero,$t5

diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s
index e0cb86d02c95a415d4e80e119a284fb883477014..f7fa2ef8350c4620ec269645ae57cc36fc78ff11 100644 (file)
--- a/test/MC/Mips/mips32r2/valid.s
+++ b/test/MC/Mips/mips32r2/valid.s
@@ -161,6 +161,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647

diff --git a/test/MC/Mips/mips4/valid-xfail.s b/test/MC/Mips/mips4/valid-xfail.s
index 9120943dce2c817f2e28d413dc03c9133116e6e2..66de33061aebf489a60946d002496470a3ac3399 100644 (file)
--- a/test/MC/Mips/mips4/valid-xfail.s
+++ b/test/MC/Mips/mips4/valid-xfail.s
@@ -47,7 +47,3 @@
        recip.s $f3,$f30
        rsqrt.d $f3,$f28
        rsqrt.s $f4,$f8
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr

diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s
index 1201346b8d1f616929d1f2b204359d4edfef9d41..426cb4cbc7c66b18eff14b16f6ed5134a09cf2a6 100644 (file)
--- a/test/MC/Mips/mips4/valid.s
+++ b/test/MC/Mips/mips4/valid.s
@@ -177,6 +177,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647

diff --git a/test/MC/Mips/mips5/valid-xfail.s b/test/MC/Mips/mips5/valid-xfail.s
index 3c211d6c05d3b2e400b97ec37ccedd72e901fe2e..997e949ae21644eba933b6d5341ebb1abf74d0cf 100644 (file)
--- a/test/MC/Mips/mips5/valid-xfail.s
+++ b/test/MC/Mips/mips5/valid-xfail.s
@@ -85,7 +85,3 @@
        rsqrt.d $f3,$f28
        rsqrt.s $f4,$f8
        sub.ps  $f5,$f14,$f26
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr

diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s
index f82181fd7c866e80b24c2d69e60e85089b0d02bc..8a4b5ebca5ae443c858c3ca2e3288e8e6e4beb24 100644 (file)
--- a/test/MC/Mips/mips5/valid.s
+++ b/test/MC/Mips/mips5/valid.s
@@ -177,6 +177,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647

diff --git a/test/MC/Mips/mips64/valid-xfail.s b/test/MC/Mips/mips64/valid-xfail.s
index 61bf0607513b84cbacf93ffce5df87b766b6f53c..610cdf796c75addf07665b7e2c36fa36efc25d21 100644 (file)
--- a/test/MC/Mips/mips64/valid-xfail.s
+++ b/test/MC/Mips/mips64/valid-xfail.s
@@ -92,7 +92,3 @@
        rsqrt.d $f3,$f28
        rsqrt.s $f4,$f8
        sub.ps  $f5,$f14,$f26
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr

diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s
index 175a317055d0b48c2e640924d36570f5162f4511..2164e2c151a000673604d4755fa3e6f711bd2e29 100644 (file)
--- a/test/MC/Mips/mips64/valid.s
+++ b/test/MC/Mips/mips64/valid.s
@@ -191,6 +191,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647

diff --git a/test/MC/Mips/mips64r2/valid-xfail.s b/test/MC/Mips/mips64r2/valid-xfail.s
index be691b16189be55484580c53c96b2180f2f222c5..1bb5ac9f671bcbcfa54326dbe1da5395aa434967 100644 (file)
--- a/test/MC/Mips/mips64r2/valid-xfail.s
+++ b/test/MC/Mips/mips64r2/valid-xfail.s
@@ -306,10 +306,6 @@
        tlbgwr
        tlbinv
        tlbinvf
-       tlbp
-       tlbr
-       tlbwi
-       tlbwr
        wrpgpr  $zero,$t5
        xor.v   $w20,$w21,$w30
        yield   $v1,$s0

diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s
index 86ed004dd78af06bc1a61f2d60e2256e5880ad0b..a136fc47cbe3e41d6f93988929781a3b1ba51b2c 100644 (file)
--- a/test/MC/Mips/mips64r2/valid.s
+++ b/test/MC/Mips/mips64r2/valid.s
@@ -213,6 +213,10 @@
        teqi    $s5,-17504
        tgei    $s1,5025
        tgeiu   $sp,-28621
+       tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+       tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+       tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+       tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
        tlti    $t6,-21059
        tltiu   $ra,-5076
        tnei    $t4,-29647