Add instruction encodings / disassembly support for 0r instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td
index f7fa673db818d3ddda1f7d16cd7ad4e16e4ce6d0..c120240d6e2b3b59f513c742a4a4e6f4a6fcc436 100644 (file)
--- a/lib/Target/XCore/XCoreInstrFormats.td
+++ b/lib/Target/XCore/XCoreInstrFormats.td
@@ -95,8 +95,11 @@ class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
   let Inst{3-0} = a;
 }
 
-class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern>
+class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstXCore<2, outs, ins, asmstr, pattern> {
+  let Inst{15-11} = opc{9-5};
+  let Inst{10-5} = 0b111111;
+  let Inst{4-0} = opc{4-0};
 }
 
 class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>

diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index e41c6d934eec044acd1631471319985f78c94df9..8254efe5382b7c24703259868386231c7655d6b3 100644 (file)
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -1018,31 +1018,31 @@ def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
 // stet, getkep, getksp, setkep, getid, kret, dcall, dret,
 // dentsp, drestsp
 
-def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>;
+def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
 
 let Defs = [R11] in {
-def GETID_0R : _F0R<(outs), (ins),
+def GETID_0R : _F0R<0b0001001110, (outs), (ins),
                     "get r11, id",
                     [(set R11, (int_xcore_getid))]>;
 
-def GETED_0R : _F0R<(outs), (ins),
+def GETED_0R : _F0R<0b0000111110, (outs), (ins),
                     "get r11, ed",
                     [(set R11, (int_xcore_geted))]>;
 
-def GETET_0R : _F0R<(outs), (ins),
+def GETET_0R : _F0R<0b0000111111, (outs), (ins),
                     "get r11, et",
                     [(set R11, (int_xcore_getet))]>;
 }
 
-def SSYNC_0r : _F0R<(outs), (ins),
+def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
                     "ssync",
                     [(int_xcore_ssync)]>;
 
 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
     hasSideEffects = 1 in
-def WAITEU_0R : _F0R<(outs), (ins),
-                 "waiteu",
-                 [(brind (int_xcore_waitevent))]>;
+def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
+                     "waiteu",
+                     [(brind (int_xcore_waitevent))]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns

diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt
index 3dacf6d3b63a1f2d3a08c593adea29b1728dbff9..45060c678ec5c29b66a6805e42da56ab5d790235 100644 (file)
--- a/test/MC/Disassembler/XCore/xcore.txt
+++ b/test/MC/Disassembler/XCore/xcore.txt
@@ -1,6 +1,26 @@
 # RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s
 # CHECK: .section        __TEXT,__text,regular,pure_instructions
 
+# 0r instructions
+
+# CHECK: clre
+0xed 0x07
+
+# CHECK: get r11, id
+0xee 0x17
+
+# CHECK: get r11, ed
+0xfe 0x0f
+
+# CHECK: get r11, et
+0xff 0x0f
+
+# CHECK: ssync
+0xee 0x07
+
+# CHECK: waiteu
+0xec 0x07
+
 # 1r instructions
 
 # CHECK: msync res[r0]