Add encoding for VSUB and VCMP.

Fear not! I'm going to try a refactoring right now. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 3fb8ebea4029b2c8ef4d3ebdba8bc986f3fe86f6..5fad39e7c98385936e6d2f586fa15b9e98aa668b 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -145,10 +145,12 @@ def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
 def VADDD  : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
                  IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
                  [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]> {
+  // Instruction operands.
   bits<5> Dd;
   bits<5> Dn;
   bits<5> Dm;
 
+  // Encode instruction operands.
   let Inst{3-0}   = Dm{3-0};
   let Inst{5}     = Dm{4};
   let Inst{19-16} = Dn{3-0};
@@ -160,10 +162,12 @@ def VADDD  : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
 def VADDS  : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                   IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
                   [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
+  // Instruction operands.
   bits<5> Sd;
   bits<5> Sn;
   bits<5> Sm;
 
+  // Encode instruction operands.
   let Inst{3-0}   = Sm{4-1};
   let Inst{5}     = Sm{0};
   let Inst{19-16} = Sn{4-1};
@@ -172,23 +176,38 @@ def VADDS  : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
   let Inst{22}    = Sd{0};
 }
 
-// These are encoded as unary instructions.
-let Defs = [FPSCR] in {
-def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins DPR:$a, DPR:$b),
-                 IIC_fpCMP64, "vcmpe", ".f64\t$a, $b",
-                 [(arm_cmpfp DPR:$a, (f64 DPR:$b))]>;
+def VSUBD  : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
+                 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
+                 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]> {
+  // Instruction operands.
+  bits<5> Dd;
+  bits<5> Dn;
+  bits<5> Dm;
 
-def VCMPD  : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
-                 IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
-                 [/* For disassembly only; pattern left blank */]>;
+  // Encode instruction operands.
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+  let Inst{19-16} = Dn{3-0};
+  let Inst{7}     = Dn{4};
+  let Inst{15-12} = Dd{3-0};
+  let Inst{22}    = Dd{4};
+}
 
-def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins SPR:$a, SPR:$b),
-                 IIC_fpCMP32, "vcmpe", ".f32\t$a, $b",
-                 [(arm_cmpfp SPR:$a, SPR:$b)]>;
+def VSUBS  : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
+                  IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
+                  [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
+  // Instruction operands.
+  bits<5> Sd;
+  bits<5> Sn;
+  bits<5> Sm;
 
-def VCMPS  : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
-                 IIC_fpCMP32, "vcmp", ".f32\t$a, $b",
-                 [/* For disassembly only; pattern left blank */]>;
+  // Encode instruction operands.
+  let Inst{3-0}   = Sm{4-1};
+  let Inst{5}     = Sm{0};
+  let Inst{19-16} = Sn{4-1};
+  let Inst{7}     = Sn{0};
+  let Inst{15-12} = Sd{4-1};
+  let Inst{22}    = Sd{0};
 }
 
 def VDIVD  : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
@@ -222,13 +241,44 @@ def : Pat<(fmul (fneg SPR:$a), SPR:$b),
           (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
 
 
-def VSUBD  : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
-                 IIC_fpALU64, "vsub", ".f64\t$dst, $a, $b",
-                 [(set DPR:$dst, (fsub DPR:$a, (f64 DPR:$b)))]>;
+// These are encoded as unary instructions.
+let Defs = [FPSCR] in {
+def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs),(ins DPR:$Dd, DPR:$Dm),
+                 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
+                 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]> {
+  // Instruction operands.
+  bits<5> Dd;
+  bits<5> Dm;
+
+  // Encode instruction operands.
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+  let Inst{15-12} = Dd{3-0};
+  let Inst{22}    = Dd{4};
+}
 
-def VSUBS  : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
-                  IIC_fpALU32, "vsub", ".f32\t$dst, $a, $b",
-                  [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
+def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs),(ins SPR:$Sd, SPR:$Sm),
+                 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
+                 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
+  // Instruction operands.
+  bits<5> Sd;
+  bits<5> Sm;
+
+  // Encode instruction operands.
+  let Inst{3-0}   = Sm{4-1};
+  let Inst{5}     = Sm{0};
+  let Inst{15-12} = Sd{4-1};
+  let Inst{22}    = Sd{0};
+}
+
+def VCMPD  : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
+                 IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
+                 [/* For disassembly only; pattern left blank */]>;
+
+def VCMPS  : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
+                 IIC_fpCMP32, "vcmp", ".f32\t$a, $b",
+                 [/* For disassembly only; pattern left blank */]>;
+}
 
 //===----------------------------------------------------------------------===//
 // FP Unary Operations.

diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
index 475a9c69caa53b9ed65cbbfc64dfa42189857019..88bf8be638d25b3c0d1f4cdfaf76b273cf2fa6dd 100644 (file)
--- a/test/MC/ARM/simple-fp-encoding.ll
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -6,18 +6,50 @@
 ;        assembly.
 
 
-define float @f1(float %a, float %b) nounwind readnone {
+define double @f1(double %a, double %b) nounwind readnone {
 entry:
 ; CHECK: f1
+; CHECK: vadd.f64 d16, d17, d16  @ encoding: [0xa0,0x0b,0x71,0xee]
+  %add = fadd double %a, %b
+  ret double %add
+}
+
+define float @f2(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f2
 ; CHECK: vadd.f32 s0, s1, s0  @ encoding: [0x80,0x0a,0x30,0xee]
   %add = fadd float %a, %b
   ret float %add
 }
 
-define double @f2(double %a, double %b) nounwind readnone {
+define double @f3(double %a, double %b) nounwind readnone {
 entry:
-; CHECK: f2
-; CHECK: vadd.f64 d16, d17, d16  @ encoding: [0xa0,0x0b,0x71,0xee]
-  %add = fadd double %a, %b
-  ret double %add
+; CHECK: f3
+; CHECK: vsub.f64 d16, d17, d16  @ encoding: [0xe0,0x0b,0x71,0xee]
+  %sub = fsub double %a, %b
+  ret double %sub
+}
+
+define float @f4(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f4
+; CHECK: vsub.f32 s0, s1, s0  @ encoding: [0xc0,0x0a,0x30,0xee]
+  %sub = fsub float %a, %b
+  ret float %sub
+}
+
+define i1 @f5(double %a, double %b) nounwind readnone {
+entry:
+; CHECK: f5
+; CHECK: vcmpe.f64 d17, d16  @ encoding: [0xe0,0x1b,0xf4,0xee]
+  %cmp = fcmp oeq double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @f6(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f6
+; CHECK: vcmpe.f32 s1, s0  @ encoding: [0xc0,0x0a,0xf4,0xee]
+  %cmp = fcmp oeq float %a, %b
+  ret i1 %cmp
 }