Preliminary mul lowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75951 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 54e3b9e69233fe4d4aa28742bcc44510792ce5cf..a5999feaa3e2a83147545dda22dd0cedfef8fbc9 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -72,6 +72,17 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
   setOperationAction(ISD::SELECT,           MVT::i64, Expand);
   setOperationAction(ISD::SELECT_CC,        MVT::i32, Custom);
   setOperationAction(ISD::SELECT_CC,        MVT::i64, Custom);
+
+  // FIXME: We can lower this better
+  setOperationAction(ISD::MULHS,            MVT::i32, Expand);
+  setOperationAction(ISD::MULHS,            MVT::i64, Expand);
+  setOperationAction(ISD::MULHU,            MVT::i32, Expand);
+  setOperationAction(ISD::MULHU,            MVT::i64, Expand);
+
+  setOperationAction(ISD::SMUL_LOHI,        MVT::i32, Expand);
+  setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Expand);
+  setOperationAction(ISD::UMUL_LOHI,        MVT::i32, Expand);
+  setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Expand);
 }
 
 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 7f0439dc086a81208c6372e3877ae5411e2da9b3..4b5a9ce3ba9b9bbb7da83e9f3715742786ef9231 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -608,6 +608,39 @@ def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
                          [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>;
 
 } // Defs = [PSW]
+
+let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
+def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+                     "msr\t{$dst, $src2}",
+                     [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
+def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+                     "msgr\t{$dst, $src2}",
+                     [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
+}
+
+def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32i16imm:$src2),
+                         "mhi\t{$dst, $src2}",
+                         [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
+def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+                         "msfi\t{$dst, $src2}",
+                         [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
+def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+                         "mghi\t{$dst, $src2}",
+                         [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
+def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
+                         "msgfi\t{$dst, $src2}",
+                         [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
+
+def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
+                     "msy\t{$dst, $src2}",
+                     [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
+def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
+                     "msgy\t{$dst, $src2}",
+                     [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
+
+def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
+                         "msgfr\t{$dst, $src2}",
+                         [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 } // isTwoAddress = 1
 
 //===----------------------------------------------------------------------===//