[AArch64] Add support for NEON scalar negate instruction.
authorChad Rosier <mcrosier@codeaurora.org>
Wed, 16 Oct 2013 21:04:39 +0000 (21:04 +0000)
committerChad Rosier <mcrosier@codeaurora.org>
Wed, 16 Oct 2013 21:04:39 +0000 (21:04 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/IR/IntrinsicsAArch64.td
lib/Target/AArch64/AArch64InstrNEON.td
test/CodeGen/AArch64/neon-scalar-neg.ll
test/MC/AArch64/neon-diagnostics.s
test/MC/AArch64/neon-scalar-neg.s
test/MC/Disassembler/AArch64/neon-instructions.txt

index d11c672ef992af08ce376b3f4e80d21947c296bf..f707df7be2bcfe12911c43e8b27f4622d071a01d 100644 (file)
@@ -200,4 +200,8 @@ def int_aarch64_neon_vsqadd : Neon_2Arg_Intrinsic;
 // Scalar Absolute Value
 def int_aarch64_neon_vabs :
   Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>;
+
+// Scalar Negate Value
+def int_aarch64_neon_vneg :
+  Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>;
 }
index 96a5482f99efed90434b35f7df583e92d0c1d90d..440e739e4bab7a7bd950a6908f7d007b0cb09250 100644 (file)
@@ -3585,6 +3585,10 @@ defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
 
+// Scalar Negate
+defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
+defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
+
 // Scalar Signed Saturating Negate
 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
index 41d48322adde10fa69770fa9345ef70946deb444..4dc9d519783db4f1b4c17a7c46d033f9ce1ddcbc 100644 (file)
@@ -1,5 +1,17 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
 
+define i64 @test_vnegd_s64(i64 %a) {
+; CHECK: test_vnegd_s64
+; CHECK: neg {{d[0-9]+}}, {{d[0-9]+}}
+entry:
+  %vneg.i = insertelement <1 x i64> undef, i64 %a, i32 0
+  %vneg1.i = tail call <1 x i64> @llvm.aarch64.neon.vneg(<1 x i64> %vneg.i)
+  %0 = extractelement <1 x i64> %vneg1.i, i32 0
+  ret i64 %0
+}
+
+declare <1 x i64> @llvm.aarch64.neon.vneg(<1 x i64>)
+
 define i8 @test_vqnegb_s8(i8 %a) {
 ; CHECK: test_vqnegb_s8
 ; CHECK: sqneg {{b[0-9]+}}, {{b[0-9]+}}
index ddd80ea1787a7cb73de8238fc5923f5a7d3146f8..411ea9fe0b11a5ec8ece60983d97a1d5a8d0ef2d 100644 (file)
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        abs d29, s24
 // CHECK-ERROR:                 ^
+
+//----------------------------------------------------------------------
+// Scalar Negate
+//----------------------------------------------------------------------
+
+    neg d29, s24
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        neg d29, s24
+// CHECK-ERROR:                 ^
index 0e637da794963f16f0c096ce27666e879e82a5fa..8e5d61dd2459c1faab3abe4baddfce28afb6695a 100644 (file)
@@ -2,6 +2,14 @@
 
 // Check that the assembler can handle the documented syntax for AArch64
 
+//----------------------------------------------------------------------
+// Scalar Negate
+//----------------------------------------------------------------------
+
+    neg d29, d24
+
+// CHECK: neg d29, d24    // encoding: [0x1d,0xbb,0xe0,0x7e]
+        
 //----------------------------------------------------------------------
 // Scalar Signed Saturating Negate
 //----------------------------------------------------------------------
index 81fffd6c7cba73fa3cf6d7f61822656f9c05922c..c70a2f6486882dbe4037765ca91334805040b0f5 100644 (file)
 0x94,0x79,0xa0,0x5e
 0x92,0x79,0xe0,0x5e
 
+#----------------------------------------------------------------------
+# Scalar Negate
+#----------------------------------------------------------------------
+# CHECK: neg d29, d24
+0x1d,0xbb,0xe0,0x7e
+
 #----------------------------------------------------------------------
 # Scalar Signed Saturating Negate
 #----------------------------------------------------------------------