powerpc/eeh: Selectively enable IO for error log
authorGavin Shan <gwshan@linux.vnet.ibm.com>
Thu, 17 Jul 2014 04:41:39 +0000 (14:41 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 5 Aug 2014 05:41:25 +0000 (15:41 +1000)
According to the experiment I did, PCI config access is blocked
on P7IOC frozen PE by hardware, but PHB3 doesn't do that. That
means we always get 0xFF's while dumping PCI config space of the
frozen PE on P7IOC. We don't have the problem on PHB3. So we have
to enable I/O prioir to collecting error log. Otherwise, meaningless
0xFF's are always returned.

The patch fixes it by EEH flag (EEH_ENABLE_IO_FOR_LOG), which is
selectively set to indicate the case for: P7IOC on PowerNV platform,
pSeries platform.

Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/eeh.h
arch/powerpc/kernel/eeh.c
arch/powerpc/platforms/powernv/eeh-powernv.c
arch/powerpc/platforms/pseries/eeh_pseries.c

index ca8aada95069af5a659ebec62f802a192ee687cc..494c3fff4623b0d52355a02c3005dd9a04cd630a 100644 (file)
@@ -34,10 +34,11 @@ struct device_node;
 #ifdef CONFIG_EEH
 
 /* EEH subsystem flags */
-#define EEH_ENABLED            0x1     /* EEH enabled          */
-#define EEH_FORCE_DISABLED     0x2     /* EEH disabled         */
-#define EEH_PROBE_MODE_DEV     0x4     /* From PCI device      */
-#define EEH_PROBE_MODE_DEVTREE 0x8     /* From device tree     */
+#define EEH_ENABLED            0x01    /* EEH enabled          */
+#define EEH_FORCE_DISABLED     0x02    /* EEH disabled         */
+#define EEH_PROBE_MODE_DEV     0x04    /* From PCI device      */
+#define EEH_PROBE_MODE_DEVTREE 0x08    /* From device tree     */
+#define EEH_ENABLE_IO_FOR_LOG  0x10    /* Enable IO for log    */
 
 /*
  * Delay for PE reset, all in ms
index 65a163fb7b6cbce72c1060b07e223b0c589f6b8c..aa33656e9a220e6b52c0a193f5218a2db40d6d03 100644 (file)
@@ -252,7 +252,7 @@ void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
         * 0xFF's is always returned from PCI config space.
         */
        if (!(pe->type & EEH_PE_PHB)) {
-               if (eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
+               if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG))
                        eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
                eeh_ops->configure_bridge(pe);
                eeh_pe_restore_bars(pe);
index 996d8844cbdfa58db8cdbc64d5ab3ab63e98bace..0401f84f7b894f3cb9ecaaacccb12b861167a928 100644 (file)
@@ -45,6 +45,9 @@
  */
 static int powernv_eeh_init(void)
 {
+       struct pci_controller *hose;
+       struct pnv_phb *phb;
+
        /* We require OPALv3 */
        if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
                pr_warning("%s: OPALv3 is required !\n", __func__);
@@ -54,6 +57,19 @@ static int powernv_eeh_init(void)
        /* Set probe mode */
        eeh_add_flag(EEH_PROBE_MODE_DEV);
 
+       /*
+        * P7IOC blocks PCI config access to frozen PE, but PHB3
+        * doesn't do that. So we have to selectively enable I/O
+        * prior to collecting error log.
+        */
+       list_for_each_entry(hose, &hose_list, list_node) {
+               phb = hose->private_data;
+
+               if (phb->model == PNV_PHB_MODEL_P7IOC)
+                       eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
+               break;
+       }
+
        return 0;
 }
 
index ba94b5b8d58cf40bd4a5a69638a55e2823d9c9ae..dd1874ca56d9d854f89b94c71be78cd48f8026f3 100644 (file)
@@ -128,7 +128,7 @@ static int pseries_eeh_init(void)
        }
 
        /* Set EEH probe mode */
-       eeh_add_flag(EEH_PROBE_MODE_DEVTREE);
+       eeh_add_flag(EEH_PROBE_MODE_DEVTREE | EEH_ENABLE_IO_FOR_LOG);
 
        return 0;
 }