Change the prototype for TargetLowering::isOperandValidForConstraint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 6f2b07bbcdf8f669f4b4dd7eb60cbe66a888de4c..f6eb5a24e523553ec15a13101c6ae888403b18cf 100644 (file)
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -694,9 +694,12 @@ public:
                                  MVT::ValueType VT) const;
   
   
-  /// isOperandValidForConstraint - Return true if the specified SDOperand is
-  /// valid for the specified target constraint letter.
-  virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
+  /// isOperandValidForConstraint - Return the specified operand (possibly
+  /// modified) if the specified SDOperand is valid for the specified target
+  /// constraint letter, otherwise return null.
+  virtual SDOperand 
+    isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
+                                SelectionDAG &DAG);
   
   //===--------------------------------------------------------------------===//
   // Scheduler hooks

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index ee1c4acad9f37cf546e427844a9875368c1f5b41..129bcd9525916be65c4b46851ceebc6fbf2e271d 100644 (file)
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1300,18 +1300,21 @@ TargetLowering::getConstraintType(char ConstraintLetter) const {
   }
 }
 
-bool TargetLowering::isOperandValidForConstraint(SDOperand Op, 
-                                                 char ConstraintLetter) {
+/// isOperandValidForConstraint - Return the specified operand (possibly
+/// modified) if the specified SDOperand is valid for the specified target
+/// constraint letter, otherwise return null.
+SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
+                                                      char ConstraintLetter,
+                                                      SelectionDAG &DAG) {
   switch (ConstraintLetter) {
-  default: return false;
+  default: return SDOperand(0,0);
   case 'i':    // Simple Integer or Relocatable Constant
   case 'n':    // Simple Integer
   case 's':    // Relocatable Constant
-    return true;   // FIXME: not right.
+    return Op;   // FIXME: not right.
   }
 }
 
-
 std::vector<unsigned> TargetLowering::
 getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                   MVT::ValueType VT) const {

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index df4e9acfa7461c5d95b593c3c07ee42af57f0b36..cf03b99979038f91c7a86fd67b78da399ca7439b 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2658,8 +2658,8 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
 }
 
 // isOperandValidForConstraint
-bool PPCTargetLowering::
-isOperandValidForConstraint(SDOperand Op, char Letter) {
+SDOperand PPCTargetLowering::
+isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
   switch (Letter) {
   default: break;
   case 'I':
@@ -2670,32 +2670,39 @@ isOperandValidForConstraint(SDOperand Op, char Letter) {
   case 'N':
   case 'O':
   case 'P': {
-    if (!isa<ConstantSDNode>(Op)) return false;  // Must be an immediate.
+    if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate.
     unsigned Value = cast<ConstantSDNode>(Op)->getValue();
     switch (Letter) {
     default: assert(0 && "Unknown constraint letter!");
     case 'I':  // "I" is a signed 16-bit constant.
-      return (short)Value == (int)Value;
+      if ((short)Value == (int)Value) return Op;
+      break;
     case 'J':  // "J" is a constant with only the high-order 16 bits nonzero.
     case 'L':  // "L" is a signed 16-bit constant shifted left 16 bits.
-      return (short)Value == 0;
+      if ((short)Value == 0) return Op;
+      break;
     case 'K':  // "K" is a constant with only the low-order 16 bits nonzero.
-      return (Value >> 16) == 0;
+      if ((Value >> 16) == 0) return Op;
+      break;
     case 'M':  // "M" is a constant that is greater than 31.
-      return Value > 31;
+      if (Value > 31) return Op;
+      break;
     case 'N':  // "N" is a positive constant that is an exact power of two.
-      return (int)Value > 0 && isPowerOf2_32(Value);
+      if ((int)Value > 0 && isPowerOf2_32(Value)) return Op;
+      break;
     case 'O':  // "O" is the constant zero. 
-      return Value == 0;
+      if (Value == 0) return Op;
+      break;
     case 'P':  // "P" is a constant whose negation is a signed 16-bit constant.
-      return (short)-Value == (int)-Value;
+      if ((short)-Value == (int)-Value) return Op;
+      break;
     }
     break;
   }
   }
   
   // Handle standard constraint letters.
-  return TargetLowering::isOperandValidForConstraint(Op, Letter);
+  return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
 }
 
 /// isLegalAddressImmediate - Return true if the integer value can be used

diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 467b3f0955d4d098952745e3aee88f786a25b435..06a51ae5eb771a0fd58d1a0094c57b8aa116a424 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -194,7 +194,8 @@ namespace llvm {
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                         MVT::ValueType VT) const;
-    bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
+    SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
+                                          SelectionDAG &DAG);
 
     /// isLegalAddressImmediate - Return true if the integer value can be used
     /// as the offset of the target addressing mode.