Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37141 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 6de6b21c78e427f0b197d8626fbd926fa10345c6..7a12dc6ca50f09b5326fc33e3d3d577ebb4f9292 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1614,6 +1614,13 @@ bool X86::isPSHUFLWMask(SDNode *N) {
 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
   if (NumElems != 2 && NumElems != 4) return false;
 
+  // Ensure this is not an mmx shuffle.
+  if (NumElems == 4 && Elems[0].getValueType() == MVT::i16)
+    return false;
+  if (NumElems == 2 && Elems[0].getValueType() == MVT::i32)
+    return false;
+  
+  
   unsigned Half = NumElems / 2;
   for (unsigned i = 0; i < Half; ++i)
     if (!isUndefOrInRange(Elems[i], 0, NumElems))
@@ -2712,7 +2719,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
     }
   }
 
-  if (NumElems == 4) {
+  if (NumElems == 4 && 
+      // Don't do this for MMX.
+      MVT::getSizeInBits(VT) != 64) {
     MVT::ValueType MaskVT = PermMask.getValueType();
     MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
     SmallVector<std::pair<int, int>, 8> Locs;