inline
MachineOperand::MachineOperand()
: opType(MO_VirtualRegister),
- value(NULL),
- regNum(0),
immedVal(0),
+ regNum(0),
isDef(false)
{}
MachineOperand::MachineOperand(MachineOperandType operandType,
Value* _val)
: opType(operandType),
- value(_val),
- regNum(0),
immedVal(0),
+ value(_val),
isDef(false)
{}
unsigned numOperands,
OpCodeMask _opCodeMask = 0x0);
inline ~MachineInstr () {}
-
- const MachineOpCode getOpCode () const { return opCode; }
-
+ const MachineOpCode getOpCode () const;
+
//
// Information about explicit operands of the instruction
//
- unsigned int getNumOperands () const { return operands.size(); }
+ unsigned int getNumOperands () const;
bool operandIsDefined(unsigned int i) const;
// Purpose:
// Representation of the sequence of machine instructions created
// for a single VM instruction. Additionally records information
+// about hidden and implicit values used by the machine instructions:
// about hidden values used by the machine instructions:
//
// "Temporary values" are intermediate values used in the machine
// no interpretation of their operands (i.e., as a TmpInstruction
// object which actually represents such a value).
//
+// (2) "Implicit uses" are values used in the VM instruction but not in
+// the machine instruction sequence
+//
//---------------------------------------------------------------------------
class MachineCodeForVMInstr: public vector<MachineInstr*>