now that all of the targets are clean w.r.t. the number of operands for each

instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22895 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 6340a153a258c864a4b525840c205c399531ddac..ae7c4d19981594319ea48d74da21c02fe4a4c3f4 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -120,14 +120,22 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
                                   std::map<ListInit*, unsigned> &ListNumbers,
                                   std::ostream &OS) {
+  int NumOperands;
+  if (Inst.hasVariableNumberOfOperands)
+    NumOperands = -1;
+  else if (!Inst.OperandList.empty())
+    // Each logical operand can be multiple MI operands.
+    NumOperands = Inst.OperandList.back().MIOperandNo +
+                  Inst.OperandList.back().MINumOperands;
+  else
+    NumOperands = 0;
+  
   OS << "  { \"";
   if (Inst.Name.empty())
     OS << Inst.TheDef->getName();
   else
     OS << Inst.Name;
-  OS << "\",\t" << -1
-     //Inst.OperandList.size()
-     << ", -1, 0, false, 0, 0, 0, 0";
+  OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, 0, 0";
 
   // Emit all of the target indepedent flags...
   if (Inst.isReturn)     OS << "|M_RET_FLAG";