Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases

should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index d95efdb809437b905b9fa14606bd825690605e82..093f599a2b99d0d5245e9aedfe029f781136648d 100644 (file)
--- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -1064,21 +1064,27 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
       printOperand(MI, OpNum, O);
       return false;
     case 'Q':
-      if (TM.getTargetData()->isLittleEndian())
+      // Print the least significant half of a register pair.
+      if (TM.getTargetData()->isBigEndian())
         break;
-      // Fallthrough
+      printOperand(MI, OpNum, O);
+      return false;
     case 'R':
-      if (TM.getTargetData()->isBigEndian())
+      // Print the most significant half of a register pair.
+      if (TM.getTargetData()->isLittleEndian())
         break;
-      // Fallthrough
-    case 'H': // Write second word of DI / DF reference.
-      // Verify that this operand has two consecutive registers.
-      if (!MI->getOperand(OpNum).isReg() ||
-          OpNum+1 == MI->getNumOperands() ||
-          !MI->getOperand(OpNum+1).isReg())
-        return true;
-      ++OpNum;   // Return the high-part.
+      printOperand(MI, OpNum, O);
+      return false;
+    case 'H':
+      break;
     }
+    // Print the second half of a register pair (for 'Q', 'R' or 'H').
+    // Verify that this operand has two consecutive registers.
+    if (!MI->getOperand(OpNum).isReg() ||
+        OpNum+1 == MI->getNumOperands() ||
+        !MI->getOperand(OpNum+1).isReg())
+      return true;
+    ++OpNum;
   }
 
   printOperand(MI, OpNum, O);