ath9k: Set appropriate bit for AR9565 in btc control register
authorBala Shanmugam <bkamatch@qca.qualcomm.com>
Mon, 15 Oct 2012 09:59:47 +0000 (15:29 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 29 Oct 2012 19:19:28 +0000 (15:19 -0400)
Signed-off-by: Bala Shanmugam <bkamatch@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_mci.c

index 6fbd376098d797593ecd1b1c416dc002a81253e9..b2b994147aeb288294e330d8cefc12ffbd502a21 100644 (file)
@@ -850,11 +850,18 @@ int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
                 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
                 SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
                 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
-                SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
-                SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
                 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
                 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
                 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
+       if (AR_SREV_9565(ah)) {
+               regval |= SM(1, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
+                         SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK);
+               REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
+                             AR_BTCOEX_CTRL2_TX_CHAIN_MASK, 0x1);
+       } else {
+               regval |= SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
+                         SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK);
+       }
 
        REG_WRITE(ah, AR_BTCOEX_CTRL, regval);