rk29: L2 Data RAM latency set to 5 cycles, suggested by zcs

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7a246d5c268cdaccfd82c3b07782d9b7b52e054f..f5e368dc0912dab82cc778552018813b7d075466 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -272,7 +272,7 @@ __v7_setup:
        bic     r5, r5, #7 << 6
        bic     r5, r5, #15
        orr     r5, r5, #3 << 6                 @ Tag RAM latency: b011 = 4 cycles
-       orr     r5, r5, #8                      @ Data RAM latency: b1000 = 9 cycles
+       orr     r5, r5, #4                      @ Data RAM latency: b0100 = 5 cycles
        mcr     p15, 1, r5, c9, c0, 2
 #endif