/// @note This has to exist, because this is a pass, but it should never be
/// used.
TargetData() : ImmutablePass(&ID) {
- llvm_report_error("ERROR: Bad TargetData ctor used. "
+ llvm_report_error("Bad TargetData ctor used. "
"Tool did not specify a TargetData to use?");
}
Input.ConstraintVT.isInteger()) ||
(OpInfo.ConstraintVT.getSizeInBits() !=
Input.ConstraintVT.getSizeInBits())) {
- llvm_report_error("llvm: error: Unsupported asm: input constraint"
+ llvm_report_error("Unsupported asm: input constraint"
" with a matching output constraint of incompatible"
" type!");
}
// Copy the output from the appropriate register. Find a register that
// we can use.
if (OpInfo.AssignedRegs.Regs.empty()) {
- llvm_report_error("llvm: error: Couldn't allocate output reg for"
+ llvm_report_error("Couldn't allocate output reg for"
" constraint '" + OpInfo.ConstraintCode + "'!");
}
|| (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
if (OpInfo.isIndirect) {
- llvm_report_error("llvm: error: "
- "Don't know how to handle tied indirect "
+ llvm_report_error("Don't know how to handle tied indirect "
"register inputs yet!");
}
RegsForValue MatchedRegs;
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
hasMemory, Ops, DAG);
if (Ops.empty()) {
- llvm_report_error("llvm: error: Invalid operand for inline asm"
+ llvm_report_error("Invalid operand for inline asm"
" constraint '" + OpInfo.ConstraintCode + "'!");
}
// Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty()) {
- llvm_report_error("llvm: error: Couldn't allocate input reg for"
+ llvm_report_error("Couldn't allocate input reg for"
" constraint '"+ OpInfo.ConstraintCode +"'!");
}
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::BFC) {
- llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
+ llvm_report_error("ARMv6t2 JIT is not yet supported.");
}
// Part of binary is determined by TableGn.