* Changed Bcc instructions to behave like BPcc instructions

* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6655 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td
index 9ec9e73879be3c3ccd830bcad465c26ec6870f0e..e55364d4cbd8e56ce7ea086c51d3d77d4d41157e 100644 (file)
--- a/lib/Target/SparcV9/SparcV9.td
+++ b/lib/Target/SparcV9/SparcV9.td
@@ -121,6 +121,7 @@ set op2 = 0b101 in {
 #endif
 
 // Section A.6: Branch on Integer condition codes (Bicc) - p146
+#if 0 // instead of using deprecated version, use the predicted version below
 set isDeprecated = 1 in {
   set op2 = 0b010 in {
     def BA     : F2_2<0b1000, "ba">;              // Branch always
@@ -141,6 +142,29 @@ set isDeprecated = 1 in {
     def BVS    : F2_2<0b0111, "bvs">;             // Branch on overflow set
   }
 }
+#endif
+
+// Using the format of A.7 instructions...
+set op2 = 0b001 in {
+  set cc = 0 in {   // BA and BN don't read condition codes
+    def BA   : F2_3<0b1000, "ba">;              // Branch always
+    def BN   : F2_3<0b0000, "bn">;              // Branch never
+  }
+  def BNE    : F2_3<0b1001, "bne">;             // Branch !=
+  def BE     : F2_3<0b0001, "be">;              // Branch ==
+  def BG     : F2_3<0b1010, "bg">;              // Branch >
+  def BLE    : F2_3<0b0010, "ble">;             // Branch <=
+  def BGE    : F2_3<0b1011, "bge">;             // Branch >=
+  def BL     : F2_3<0b0011, "bl">;              // Branch <
+  def BGU    : F2_3<0b1100, "bgu">;             // Branch unsigned >
+  def BLEU   : F2_3<0b0100, "bleu">;            // Branch unsigned <=
+  def BCC    : F2_3<0b1101, "bcc">;             // Branch unsigned >=
+  def BCS    : F2_3<0b0101, "bcs">;             // Branch unsigned <=
+  def BPOS   : F2_3<0b1110, "bpos">;            // Branch on positive
+  def BNEG   : F2_3<0b0110, "bneg">;            // Branch on negative
+  def BVC    : F2_3<0b1111, "bvc">;             // Branch on overflow clear
+  def BVS    : F2_3<0b0111, "bvs">;             // Branch on overflow set
+}
 
 // Section A.7: Branch on integer condition codes with prediction - p148
 // Not used in the Sparc backend
@@ -669,28 +693,20 @@ set x = 0 in {
 #endif
 
 // uses 6 least significant bits of rs2
+set x = 0 in { 
+  def SLLr5  : F3_11<2, 0b100101, "sll">;                // sll r, r, r
+  def SRLr5  : F3_11<2, 0b100110, "srl">;                // srl r, r, r
+  def SRAr5  : F3_11<2, 0b100111, "sra">;                // sra r, r, r
+}
 set x = 1 in {
-  def SLLr6  : F3_11<2, 0b100101, "sll">;                // sll r, r, r
-  def SRLr6  : F3_11<2, 0b100110, "srl">;                // srl r, r, r
-  def SRAr6  : F3_11<2, 0b100111, "sra">;                // sra r, r, r
   def SLLXr6 : F3_11<2, 0b100101, "sllx">;               // sllx r, r, r
   def SRLXr6 : F3_11<2, 0b100110, "srlx">;               // srlx r, r, r
   def SRAXr6 : F3_11<2, 0b100111, "srax">;               // srax r, r, r
 }
 
-// Not currently used in the Sparc backend
-#if 0
 def SLLi5  : F3_12<2, 0b100101, "sll">;                // sll r, shcnt32, r
 def SRLi5  : F3_12<2, 0b100110, "srl">;                // srl r, shcnt32, r
 def SRAi5  : F3_12<2, 0b100111, "sra">;                // sra r, shcnt32, r
-def SLLXi5 : F3_12<2, 0b100101, "sllx">;               // sllx r, shcnt32, r
-def SRLXi5 : F3_12<2, 0b100110, "srlx">;               // srlx r, shcnt32, r
-def SRAXi5 : F3_12<2, 0b100111, "srax">;               // srax r, shcnt32, r
-#endif
-
-def SLLi6  : F3_13<2, 0b100101, "sll">;                  // sll r, shcnt64, r
-def SRLi6  : F3_13<2, 0b100110, "srl">;                  // srl r, shcnt64, r
-def SRAi6  : F3_13<2, 0b100111, "sra">;                  // sra r, shcnt64, r
 def SLLXi6 : F3_13<2, 0b100101, "sllx">;                 // sllx r, shcnt64, r
 def SRLXi6 : F3_13<2, 0b100110, "srlx">;                 // srlx r, shcnt64, r
 def SRAXi6 : F3_13<2, 0b100111, "srax">;                 // srax r, shcnt64, r
@@ -754,3 +770,9 @@ def SUBCccr : F3_1<2, 0b011100, "subccc">;                // subccc r, r, r
 def SUBCcci : F3_2<2, 0b011100, "subccc">;                // subccc r, i, r
 
 // FIXME: More...?
+
+// Section A.63: Write State Register - p244
+set rd = 2 in {
+  def WRCCRr : F3_1<2, 0b110000, "wr">;                 // wr r, r, %y/ccr/etc
+  def WRCCRi : F3_2<2, 0b110000, "wr">;                 // wr r, i, %y/ccr/etc
+}

diff --git a/lib/Target/SparcV9/SparcV9Instr.def b/lib/Target/SparcV9/SparcV9Instr.def
index 4ab37bdd5621a0e335f76a3f3fdb2d0e82dd57bf..b537bc63d7d3d02a1b3107906b6b7b4a49962008 100644 (file)
--- a/lib/Target/SparcV9/SparcV9Instr.def
+++ b/lib/Target/SparcV9/SparcV9Instr.def
@@ -135,12 +135,12 @@ I(XNORccr, "xnorcc",      4,  2, B12, true , 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICA
 I(XNORcci, "xnorcc",   4,  2, B12, true , 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG)
 
 // Shift operations
-I(SLLr6 , "sll",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SLLi6 , "sll",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLr6 , "srl",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLi6 , "srl",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRAr6 , "sra",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
-I(SRAi6 , "sra",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
+I(SLLr5 , "sll",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SLLi5 , "sll",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SRLr5 , "srl",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SRLi5 , "srl",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SRAr5 , "sra",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
+I(SRAi5 , "sra",       3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
 I(SLLXr6, "sllx",      3,  2,  B6, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
 I(SLLXi6, "sllx",      3,  2,  B6, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
 I(SRLXr6, "srlx",      3,  2,  B6, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
@@ -526,7 +526,8 @@ I(RESTOREi, "restore",      3,  2, B12, true , 0, 1,  SPARC_SINGLE, M_INT_FLAG | M_AR
 
 // Read and Write CCR register from/to an int reg
 I(RDCCR,  "rd",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
-I(WRCCR,  "wr",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
+I(WRCCRr,  "wr",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
+I(WRCCRi,  "wr",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
 
 // Synthetic phi operation for near-SSA form of machine code
 // Number of operands is variable, indicated by -1.  Result is the first op.

diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index 57ce3cd36a70012b1d19844ea76fef4db1f4f820..25d4627c06a15d3b71e12f3b5d3ac769f15178ee 100644 (file)
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -145,7 +145,7 @@ CreateSETSWConst(const TargetMachine& target, int32_t C,
   // Sign-extend to the high 32 bits if needed.
   // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
   if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
-    mvec.push_back(BuildMI(V9::SRAi6, 3).addReg(dest).addZImm(0).addRegDef(dest));
+    mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
 }
 
 
@@ -692,7 +692,7 @@ CreateBitExtensionInstructions(bool signExtend,
     srcVal = tmpI;
   }
 
-  mvec.push_back(BuildMI(signExtend? V9::SRAi6 : V9::SRLi6, 3)
+  mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
                  .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
 }
 

diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
index db49c4ebde230c8f5c0565bd57e48198a40499b7..e5ea7e82b2ddc70646cce75df63454c70ee1944f 100644 (file)
--- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
@@ -747,7 +747,7 @@ CreateShiftInstructions(const TargetMachine& target,
   Value* shiftDest = destVal;
   unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
 
-  if ((shiftOpCode == V9::SLLr6 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
+  if ((shiftOpCode == V9::SLLr5 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
     // put SLL result into a temporary
     shiftDest = new TmpInstruction(mcfi, argVal1, optArgVal2, "sllTmp");
   }
@@ -815,7 +815,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
         mvec.push_back(M);
       } else if (isPowerOf2(C, pow)) {
         unsigned opSize = target.getTargetData().getTypeSize(resultType);
-        MachineOpCode opCode = (opSize <= 32)? V9::SLLr6 : V9::SLLXr6;
+        MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
         CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
                                 destVal, mvec, mcfi);
       }
@@ -979,7 +979,7 @@ CreateDivConstInstruction(TargetMachine &target,
 
           // Create the SRL or SRLX instruction to get the sign bit
           mvec.push_back(BuildMI((resultType==Type::LongTy) ?
-                                 V9::SRLXi6 : V9::SRLi6, 3)
+                                 V9::SRLXi6 : V9::SRLi5, 3)
                          .addReg(LHS)
                          .addSImm((resultType==Type::LongTy)? 63 : 31)
                          .addRegDef(srlTmp));
@@ -990,11 +990,11 @@ CreateDivConstInstruction(TargetMachine &target,
 
           // Get the shift operand and "right-shift" opcode to do the divide
           shiftOperand = addTmp;
-          opCode = (resultType==Type::LongTy) ? V9::SRAXi6 : V9::SRAi6;
+          opCode = (resultType==Type::LongTy) ? V9::SRAXi6 : V9::SRAi5;
         } else {
           // Get the shift operand and "right-shift" opcode to do the divide
           shiftOperand = LHS;
-          opCode = (resultType==Type::LongTy) ? V9::SRLXi6 : V9::SRLi6;
+          opCode = (resultType==Type::LongTy) ? V9::SRLXi6 : V9::SRLi5;
         }
 
         // Now do the actual shift!
@@ -2419,7 +2419,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
                "Shl unsupported for other types");
         
         CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
-                                (opType == Type::LongTy)? V9::SLLXr6:V9::SLLr6,
+                                (opType == Type::LongTy)? V9::SLLXr6:V9::SLLr5,
                                 argVal1, argVal2, 0, shlInstr, mvec,
                                 MachineCodeForInstruction::get(shlInstr));
         break;
@@ -2431,8 +2431,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         assert((opType->isInteger() || isa<PointerType>(opType)) &&
                "Shr unsupported for other types");
         Add3OperandInstr(opType->isSigned()
-                         ? (opType == Type::LongTy ? V9::SRAXr6 : V9::SRAr6)
-                         : (opType == Type::LongTy ? V9::SRLXr6 : V9::SRLr6),
+                         ? (opType == Type::LongTy ? V9::SRAXr6 : V9::SRAr5)
+                         : (opType == Type::LongTy ? V9::SRLXr6 : V9::SRLr5),
                          subtreeRoot, mvec);
         break;
       }
@@ -2503,7 +2503,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         for (unsigned i=0, N=mvec.size(); i < N; ++i)
           mvec[i]->substituteValue(dest, tmpI);
 
-        M = BuildMI(V9::SRLi6, 3).addReg(tmpI).addZImm(8*(4-destSize))
+        M = BuildMI(V9::SRLi5, 3).addReg(tmpI).addZImm(8*(4-destSize))
           .addReg(dest, MOTy::Def);
         mvec.push_back(M);
       } else if (destSize < 8) {

diff --git a/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h b/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h
index 7f9bdc8e8b23279cbfb88ff31d42ffd06224648c..1be1de10448cf78ac98e521012cc5a5271707f45 100644 (file)
--- a/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h
+++ b/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h
@@ -110,9 +110,9 @@ convertOpcodeFromRegToImm(unsigned Opcode) {
   case V9::XNORccr: return V9::XNORcci;
 
     /* shift */
-  case V9::SLLr6:   return V9::SLLi6;
-  case V9::SRLr6:   return V9::SRLi6;
-  case V9::SRAr6:   return V9::SRAi6;
+  case V9::SLLr5:   return V9::SLLi5;
+  case V9::SRLr5:   return V9::SRLi5;
+  case V9::SRAr5:   return V9::SRAi5;
   case V9::SLLXr6:  return V9::SLLXi6;
   case V9::SRLXr6:  return V9::SRLXi6;
   case V9::SRAXr6:  return V9::SRAXi6;

diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index 5aa74f36052c37a23641cac0e677f816adb1020d..babb4709db025871230d29287af6319cc904a352 100644 (file)
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -86,7 +86,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
     M->setOperandLo32(1);
     mvec.push_back(M);
     
-    M = BuildMI(V9::SRAi6, 3).addMReg(uregNum).addZImm(0)
+    M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
       .addMReg(uregNum, MOTy::Def);
     mvec.push_back(M);
     

diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 1cc274de00f76619adf53c8ff1d22bb6b82f7c68..780a5578c8833d7cb6bc24b58dd91ad7f33330b5 100644 (file)
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -1068,7 +1068,8 @@ UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
                                unsigned SrcReg,
                                unsigned DestReg,
                                int RegType) const {
-  assert( ((int)SrcReg != getInvalidRegNum()) && ((int)DestReg != getInvalidRegNum()) &&
+  assert( ((int)SrcReg != getInvalidRegNum()) && 
+          ((int)DestReg != getInvalidRegNum()) &&
          "Invalid Register");
   
   MachineInstr * MI = NULL;
@@ -1085,7 +1086,8 @@ UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
       // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
       assert(getRegType(SrcReg) == IntRegType
              && "Can only copy CC reg to/from integer reg");
-      MI = BuildMI(V9::WRCCR, 2).addMReg(SrcReg).addMReg(DestReg+1, MOTy::Def);
+      MI = BuildMI(V9::WRCCRr, 2).addMReg(SrcReg)
+        .addMReg(SparcIntRegClass::g0).addMReg(DestReg+1, MOTy::Def);
     }
     break;
     
@@ -1212,7 +1214,8 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
     cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
     
     // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
-    MI = BuildMI(V9::WRCCR, 2).addMReg(scratchReg).addMReg(DestReg+1,MOTy::Def);
+    MI = BuildMI(V9::WRCCRr, 2).addMReg(scratchReg)
+      .addMReg(SparcIntRegClass::g0).addMReg(DestReg+1,MOTy::Def);
     break;
     
   case FloatCCRegType: {