Vector op lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 154fe177ba1b0ccf51b518c59cb3bac92ee26d14..204a45a4f9dc0f2dbd9e9a493a0bb1a3a729f0ce 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -156,10 +156,26 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
     setOperationAction(ISD::SRA, MVT::i64, Custom);
   }
   
+  // First set operation action for all vector types to expand. Then we
+  // will selectively turn on ones that can be effectively codegen'd.
+  for (unsigned VT = (unsigned)MVT::Vector + 1;
+       VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
+    setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
+  }
+
   if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
     addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
     addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
     
+    setOperationAction(ISD::ADD        , MVT::v4f32, Legal);
+    setOperationAction(ISD::SUB        , MVT::v4f32, Legal);
+    setOperationAction(ISD::MUL        , MVT::v4f32, Legal);
+    setOperationAction(ISD::LOAD       , MVT::v4f32, Legal);
+    setOperationAction(ISD::ADD        , MVT::v4i32, Legal);
+    setOperationAction(ISD::LOAD       , MVT::v4i32, Legal);
     // FIXME: We don't support any ConstantVec's yet.  We should custom expand
     // the ones we do!
     setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 48e049c6175edd77d6303d6b78fe865ec0ff74c3..2fd848d0306d2ef82927a10475081935bf882160 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -238,13 +238,22 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     addLegalFPImmediate(-1.0); // FLD1/FCHS
   }
 
+  // First set operation action for all vector types to expand. Then we
+  // will selectively turn on ones that can be effectively codegen'd.
+  for (unsigned VT = (unsigned)MVT::Vector + 1;
+       VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
+    setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
+  }
+
   if (TM.getSubtarget<X86Subtarget>().hasMMX()) {
     addRegisterClass(MVT::v8i8,  X86::VR64RegisterClass);
     addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
     addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
 
-    // FIXME: We don't support any ConstantVec's yet.  We should custom expand
-    // the ones we do!
+    // FIXME: add MMX packed arithmetics
     setOperationAction(ISD::ConstantVec, MVT::v8i8,  Expand);
     setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
     setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
@@ -253,8 +262,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   if (TM.getSubtarget<X86Subtarget>().hasSSE1()) {
     addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
 
-    // FIXME: We don't support any ConstantVec's yet.  We should custom expand
-    // the ones we do!
+    setOperationAction(ISD::ADD        , MVT::v4f32, Legal);
+    setOperationAction(ISD::SUB        , MVT::v4f32, Legal);
+    setOperationAction(ISD::MUL        , MVT::v4f32, Legal);
+    setOperationAction(ISD::LOAD       , MVT::v4f32, Legal);
     setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
   }
 
@@ -266,8 +277,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
 
 
-    // FIXME: We don't support any ConstantVec's yet.  We should custom expand
-    // the ones we do!
+    setOperationAction(ISD::ADD        , MVT::v2f64, Legal);
+    setOperationAction(ISD::SUB        , MVT::v2f64, Legal);
+    setOperationAction(ISD::MUL        , MVT::v2f64, Legal);
+    setOperationAction(ISD::LOAD       , MVT::v2f64, Legal);
     setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
     setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
     setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);