Move pass configuration out of pass constructors: TailDuplicate::PreRegAlloc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150091 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 30abcd7b9254ccd2f323999474f1385ef9e1d208..2585aebc1c01bca5055593b1e15c10294930492e 100644 (file)
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -272,7 +272,7 @@ namespace llvm {
 
   /// TailDuplicate Pass - Duplicate blocks with unconditional branches
   /// into tails of their predecessors.
-  FunctionPass *createTailDuplicatePass(bool PreRegAlloc = false);
+  FunctionPass *createTailDuplicatePass();
 
   /// IfConverter Pass - This pass performs machine code if conversion.
   FunctionPass *createIfConverterPass();

diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp
index 21d87143fef49c1172d956f4f366d2cbf9fccfad..eb5673498302859ebc3a0196b74322aafd7185a1 100644 (file)
--- a/lib/CodeGen/Passes.cpp
+++ b/lib/CodeGen/Passes.cpp
@@ -178,7 +178,7 @@ void TargetPassConfig::addMachinePasses() {
 
   // Pre-ra tail duplication.
   if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
-    PM.add(createTailDuplicatePass(true));
+    PM.add(createTailDuplicatePass());
     printAndVerify("After Pre-RegAlloc TailDuplicate");
   }
 
@@ -250,7 +250,7 @@ void TargetPassConfig::addMachinePasses() {
 
   // Tail duplication.
   if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
-    PM.add(createTailDuplicatePass(false));
+    PM.add(createTailDuplicatePass());
     printNoVerify("After TailDuplicate");
   }
 

diff --git a/lib/CodeGen/TailDuplication.cpp b/lib/CodeGen/TailDuplication.cpp
index 031377b36b5435aef63f5f083acf975e65cf0638..ac4e2c452523a2f031f01de93c36f8a7f576265a 100644 (file)
--- a/lib/CodeGen/TailDuplication.cpp
+++ b/lib/CodeGen/TailDuplication.cpp
@@ -56,10 +56,10 @@ typedef std::vector<std::pair<MachineBasicBlock*,unsigned> > AvailableValsTy;
 namespace {
   /// TailDuplicatePass - Perform tail duplication.
   class TailDuplicatePass : public MachineFunctionPass {
-    bool PreRegAlloc;
     const TargetInstrInfo *TII;
     MachineModuleInfo *MMI;
     MachineRegisterInfo *MRI;
+    bool PreRegAlloc;
 
     // SSAUpdateVRs - A list of virtual registers for which to update SSA form.
     SmallVector<unsigned, 16> SSAUpdateVRs;
@@ -70,8 +70,8 @@ namespace {
 
   public:
     static char ID;
-    explicit TailDuplicatePass(bool PreRA) :
-      MachineFunctionPass(ID), PreRegAlloc(PreRA) {}
+    explicit TailDuplicatePass() :
+      MachineFunctionPass(ID), PreRegAlloc(false) {}
 
     virtual bool runOnMachineFunction(MachineFunction &MF);
     virtual const char *getPassName() const { return "Tail Duplication"; }
@@ -118,14 +118,15 @@ namespace {
   char TailDuplicatePass::ID = 0;
 }
 
-FunctionPass *llvm::createTailDuplicatePass(bool PreRegAlloc) {
-  return new TailDuplicatePass(PreRegAlloc);
+FunctionPass *llvm::createTailDuplicatePass() {
+  return new TailDuplicatePass();
 }
 
 bool TailDuplicatePass::runOnMachineFunction(MachineFunction &MF) {
   TII = MF.getTarget().getInstrInfo();
   MRI = &MF.getRegInfo();
   MMI = getAnalysisIfAvailable<MachineModuleInfo>();
+  PreRegAlloc = MRI->isSSA();
 
   bool MadeChange = false;
   while (TailDuplicateBlocks(MF))
@@ -823,7 +824,7 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,
   SmallVector<MachineOperand, 4> PriorCond;
   // This has to check PrevBB->succ_size() because EH edges are ignored by
   // AnalyzeBranch.
-  if (PrevBB->succ_size() == 1 && 
+  if (PrevBB->succ_size() == 1 &&
       !TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) &&
       PriorCond.empty() && !PriorTBB && TailBB->pred_size() == 1 &&
       !TailBB->hasAddressTaken()) {

diff --git a/lib/Target/PTX/PTXTargetMachine.cpp b/lib/Target/PTX/PTXTargetMachine.cpp
index 4ffd01b75a63da3ec9e0fa04a71b9145a343b426..8901fa0b973fbf0d3fe4cf1f461de6914e0e647c 100644 (file)
--- a/lib/Target/PTX/PTXTargetMachine.cpp
+++ b/lib/Target/PTX/PTXTargetMachine.cpp
@@ -284,7 +284,7 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
 
   // Pre-ra tail duplication.
   if (getOptLevel() != CodeGenOpt::None) {
-    PM.add(createTailDuplicatePass(true));
+    PM.add(createTailDuplicatePass());
     printAndVerify("After Pre-RegAlloc TailDuplicate");
   }
 
@@ -365,7 +365,7 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
 
   // Tail duplication.
   if (getOptLevel() != CodeGenOpt::None) {
-    PM.add(createTailDuplicatePass(false));
+    PM.add(createTailDuplicatePass());
     printNoVerify("After TailDuplicate");
   }