- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset

  is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77701 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 89127edbe33770bc374773c908aeeb1005422dcb..471da050f1ecd46f25a62fe555a27e3ce6792efe 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -446,9 +446,14 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
     case ARM::BR_JTr:
     case ARM::BR_JTm:
     case ARM::BR_JTadd:
-    case ARM::t2BR_JT: {
+    case ARM::t2BR_JT:
+    case ARM::t2TBB:
+    case ARM::t2TBH: {
       // These are jumptable branches, i.e. a branch followed by an inlined
-      // jumptable. The size is 4 + 4 * number of entries.
+      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
+      // entry is one byte; TBH two byte each.
+      unsigned EntrySize = (MI->getOpcode() == ARM::t2TBB)
+        ? 1 : ((MI->getOpcode() == ARM::t2TBH) ? 2 : 4);
       unsigned NumOps = TID.getNumOperands();
       MachineOperand JTOP =
         MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
@@ -463,7 +468,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
       // FIXME: If we know the size of the function is less than (1 << 16) *2
       // bytes, we can use 16-bit entries instead. Then there won't be an
       // alignment issue.
-      return getNumJTEntries(JT, JTI) * 4 + (IsThumb1JT ? 2 : 4);
+      return getNumJTEntries(JT, JTI) * EntrySize + (IsThumb1JT ? 2 : 4);
     }
     default:
       // Otherwise, pseudo-instruction sizes are zero.

diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index bc9e11badeacae8dd6e681db22e9f52860c8165a..bf2784a54da025efea8ceee651f1150d5ba89672 100644 (file)
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -237,10 +237,10 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
   // the numbers agree with the position of the block in the function.
   MF.RenumberBlocks();
 
-  // Thumb1 functions containing constant pools get 2-byte alignment.
+  // Thumb1 functions containing constant pools get 4-byte alignment.
   // This is so we can keep exact track of where the alignment padding goes.
 
-  // Set default. Thumb1 function is 1-byte aligned, ARM and Thumb2 are 2-byte
+  // Set default. Thumb1 function is 2-byte aligned, ARM and Thumb2 are 4-byte
   // aligned.
   AFI->setAlign(isThumb1 ? 1U : 2U);
 
@@ -1360,10 +1360,9 @@ bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
       unsigned DstOffset = BBOffsets[MBB->getNumber()];
       // Negative offset is not ok. FIXME: We should change BB layout to make
       // sure all the branches are forward.
-      if (ByteOk && !OffsetIsInRange(JTOffset, DstOffset, (1<<8)-1, false))
+      if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
         ByteOk = false;
-      if (HalfWordOk &&
-          !OffsetIsInRange(JTOffset, DstOffset, (1<<16)-1, false))
+      if (HalfWordOk && (DstOffset - JTOffset) > ((1<<16)-1)*2)
         HalfWordOk = false;
       if (!ByteOk && !HalfWordOk)
         break;
@@ -1415,7 +1414,8 @@ bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
                        .addReg(IdxReg, getKillRegState(IdxRegKill))
                        .addJumpTableIndex(JTI, JTOP.getTargetFlags())
                        .addImm(MI->getOperand(JTOpIdx+1).getImm()));
-
+        // FIXME: Insert an "ALIGN" instruction to ensure the next instruction
+        // is 2-byte aligned. For now, asm printer will fix it up.
         AddrMI->eraseFromParent();
         if (LeaMI)
           LeaMI->eraseFromParent();