drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker

commit 354da653233898ed1e51f20cebac9705456bf9b1 upstream.

macro tile heights are aligned to num channels, not num banks.

Noticed by Dave Airlie.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 250a3a918193e9821aa6f5836d463553cf6f903d..478fddf08f9a1f5250e15922045b84c0104204ec 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -228,7 +228,7 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
                                __func__, __LINE__, pitch);
                        return -EINVAL;
                }
-               if (!IS_ALIGNED((height / 8), track->nbanks)) {
+               if (!IS_ALIGNED((height / 8), track->npipes)) {
                        dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
                                 __func__, __LINE__, height);
                        return -EINVAL;
@@ -367,7 +367,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
                                                 __func__, __LINE__, pitch);
                                        return -EINVAL;
                                }
-                               if ((height / 8) & (track->nbanks - 1)) {
+                               if (!IS_ALIGNED((height / 8), track->npipes)) {
                                        dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
                                                 __func__, __LINE__, height);
                                        return -EINVAL;