CR registers are not used by this "target"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23552 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Skeleton/Skeleton.td b/lib/Target/Skeleton/Skeleton.td
index 93ae184062e9c23ba27eb60c3fdb89f85e81dbe4..8a2dc7291f7eaf6fda19bedc2e7822e391a132ba 100644 (file)
--- a/lib/Target/Skeleton/Skeleton.td
+++ b/lib/Target/Skeleton/Skeleton.td
@@ -33,7 +33,7 @@ def Skeleton : Target {
   let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
     R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
     F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
-    F30, F31, CR2, CR3, CR4];
+    F30, F31];
 
   // Pull in Instruction Info:
   let InstructionSet = SkeletonInstrInfo;

diff --git a/lib/Target/Skeleton/SkeletonRegisterInfo.td b/lib/Target/Skeleton/SkeletonRegisterInfo.td
index 45856e01d03ecb605497ee08c511e0d281ef4956..5313001ae55646a003b47530c36f0324afc050ff 100644 (file)
--- a/lib/Target/Skeleton/SkeletonRegisterInfo.td
+++ b/lib/Target/Skeleton/SkeletonRegisterInfo.td
@@ -75,13 +75,6 @@ def F26 : FPR<26, "F26">;  def F27 : FPR<27, "F27">;
 def F28 : FPR<28, "F28">;  def F29 : FPR<29, "F29">;
 def F30 : FPR<30, "F30">;  def F31 : FPR<31, "F31">;
 
-
-// Condition registers
-def CR0 : CR<0, "CR0">; def CR1 : CR<1, "CR1">;
-def CR2 : CR<2, "CR2">; def CR3 : CR<3, "CR3">;
-def CR4 : CR<4, "CR4">; def CR5 : CR<5, "CR5">;
-def CR6 : CR<6, "CR6">; def CR7 : CR<7, "CR7">;
-
 // Floating-point status and control register
 def FPSCR : SPR<0, "FPSCR">;
 // fiXed-point Exception Register? :-)