enum {
Token,
Register,
+ Immediate,
Memory
} Kind;
bool Writeback;
} Reg;
+ struct {
+ const MCExpr *Val;
+ } Imm;
+
// This is for all forms of ARM address expressions
struct {
unsigned BaseRegNum;
return Reg.RegNum;
}
+ const MCExpr *getImm() const {
+ assert(Kind == Immediate && "Invalid access!");
+ return Imm.Val;
+ }
+
bool isToken() const {return Kind == Token; }
bool isReg() const { return Kind == Register; }
return Res;
}
+ static ARMOperand CreateImm(const MCExpr *Val) {
+ ARMOperand Res;
+ Res.Kind = Immediate;
+ Res.Imm.Val = Val;
+ return Res;
+ }
+
static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
const MCExpr *Offset, unsigned OffsetRegNum,
bool OffsetRegShifted, enum ShiftType ShiftType,
// for now.
bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
assert(getLexer().getTok().is(AsmToken::LCurly) &&
- "Token is not an Left Curly Brace");
+ "Token is not an Left Curly Brace");
getLexer().Lex(); // Eat left curly brace token.
const AsmToken &RegTok = getLexer().getTok();
Mnemonic == "str" ||
Mnemonic == "ldmfd" ||
Mnemonic == "ldr" ||
- Mnemonic == "mov")
+ Mnemonic == "mov" ||
+ Mnemonic == "sub")
return false;
return true;
return false;
case AsmToken::LCurly:
if (!ParseRegisterList(Op))
- return(false);
+ return false;
case AsmToken::Hash:
- return Error(getLexer().getTok().getLoc(), "immediates not yet supported");
+ // $42 -> immediate.
+ getLexer().Lex();
+ const MCExpr *Val;
+ if (getParser().ParseExpression(Val))
+ return true;
+ Op = ARMOperand::CreateImm(Val);
+ return false;
default:
return Error(getLexer().getTok().getLoc(), "unexpected token in operand");
}