misched prep: rename InsertPos to End.

ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 39a1e66256912563638fa00606bca891e8f0cb53..cf6af4bfdef750fb4cb9d62505c8bfd5ea02a5c5 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -226,7 +226,7 @@ void ScheduleTopDownLive::schedule() {
       releaseNode(&(*I));
   }
 
-  InsertPos = Begin;
+  MachineBasicBlock::iterator InsertPos = Begin;
   while (SUnit *SU = pickNode()) {
     DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
 

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index cec3223ff3a4c30a93050a1758d33c5712b1eaf7..c00cf0e0439c146ebd63f6d0e6312fab4339569c 100644 (file)
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -365,8 +365,8 @@ void SchedulePostRATDList::schedule() {
 
   if (AntiDepBreak != NULL) {
     unsigned Broken =
-      AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
-                                          InsertPosIndex, DbgValues);
+      AntiDepBreak->BreakAntiDependencies(SUnits, Begin, End, EndIndex,
+                                          DbgValues);
 
     if (Broken != 0) {
       // We made changes. Update the dependency graph.
@@ -396,7 +396,7 @@ void SchedulePostRATDList::schedule() {
 ///
 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
   if (AntiDepBreak != NULL)
-    AntiDepBreak->Observe(MI, Count, InsertPosIndex);
+    AntiDepBreak->Observe(MI, Count, EndIndex);
 }
 
 /// FinishBlock - Clean up register live-range state.
@@ -761,24 +761,24 @@ void SchedulePostRATDList::ListScheduleTopDown() {
 
 // EmitSchedule - Emit the machine code in scheduled order.
 void SchedulePostRATDList::EmitSchedule() {
-  Begin = InsertPos;
+  Begin = End;
 
   // If first instruction was a DBG_VALUE then put it back.
   if (FirstDbgValue)
-    BB->splice(InsertPos, BB, FirstDbgValue);
+    BB->splice(End, BB, FirstDbgValue);
 
   // Then re-insert them according to the given schedule.
   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
     if (SUnit *SU = Sequence[i])
-      BB->splice(InsertPos, BB, SU->getInstr());
+      BB->splice(End, BB, SU->getInstr());
     else
       // Null SUnit* is a noop.
-      TII->insertNoop(*BB, InsertPos);
+      TII->insertNoop(*BB, End);
 
     // Update the Begin iterator, as the first instruction in the block
     // may have been scheduled later.
     if (i == 0)
-      Begin = prior(InsertPos);
+      Begin = prior(End);
   }
 
   // Reinsert any remaining debug_values.

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index ef63776d6e23dc9ee2d80c2d3950642fcffafa2b..505d56c79ec1589b3ac8af46bf1732a723238e3a 100644 (file)
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -160,8 +160,8 @@ void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
                                     unsigned endcount) {
   BB = bb;
   Begin = begin;
-  InsertPos = end;
-  InsertPosIndex = endcount;
+  End = end;
+  EndIndex = endcount;
 
   // Check to see if the scheduler cares about latencies.
   UnitLatencies = forceUnitLatencies();
@@ -184,7 +184,7 @@ void ScheduleDAGInstrs::exitRegion() {
 /// are too high to be hidden by the branch or when the liveout registers
 /// used by instructions in the fallthrough block.
 void ScheduleDAGInstrs::addSchedBarrierDeps() {
-  MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
+  MachineInstr *ExitMI = End != BB->end() ? &*End : 0;
   ExitSU.setInstr(ExitMI);
   bool AllDepKnown = ExitMI &&
     (ExitMI->isCall() || ExitMI->isBarrier());
@@ -476,7 +476,7 @@ void ScheduleDAGInstrs::initSUnits() {
   // which is contained within a basic block.
   SUnits.reserve(BB->size());
 
-  for (MachineBasicBlock::iterator I = Begin; I != InsertPos; ++I) {
+  for (MachineBasicBlock::iterator I = Begin; I != End; ++I) {
     MachineInstr *MI = I;
     if (MI->isDebugValue())
       continue;
@@ -534,7 +534,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA) {
 
   // Walk the list of instructions, from bottom moving up.
   MachineInstr *PrevMI = NULL;
-  for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
+  for (MachineBasicBlock::iterator MII = End, MIE = Begin;
        MII != MIE; --MII) {
     MachineInstr *MI = prior(MII);
     if (MI && PrevMI) {

diff --git a/lib/CodeGen/ScheduleDAGInstrs.h b/lib/CodeGen/ScheduleDAGInstrs.h
index 91b7350ab1f84ae7fe8b48c3207d6dbc37344999..ace97d8ff85c0bfb58c1c2cc0d1b0af1101d51ac 100644 (file)
--- a/lib/CodeGen/ScheduleDAGInstrs.h
+++ b/lib/CodeGen/ScheduleDAGInstrs.h
@@ -119,16 +119,14 @@ namespace llvm {
     // The block in which to insert instructions
     MachineBasicBlock *BB;
 
-    // The beginning of the range to
-    // be scheduled. The range extends
-    // to InsertPos.
+    /// The beginning of the range to be scheduled.
     MachineBasicBlock::iterator Begin;
 
-    // The position to insert instructions
-    MachineBasicBlock::iterator InsertPos;
+    /// The end of the range to be scheduled.
+    MachineBasicBlock::iterator End;
 
-    // The index in BB of InsertPos.
-    unsigned InsertPosIndex;
+    /// The index in BB of End.
+    unsigned EndIndex;
 
     /// After calling BuildSchedGraph, each machine instruction in the current
     /// scheduling region is mapped to an SUnit.
@@ -239,7 +237,7 @@ namespace llvm {
     MachineBasicBlock::iterator begin() const { return Begin; }
 
     /// end - Return an iterator to the bottom of the current scheduling region.
-    MachineBasicBlock::iterator end() const { return InsertPos; }
+    MachineBasicBlock::iterator end() const { return End; }
 
     /// NewSUnit - Creates a new SUnit and return a ptr to it.
     ///