Update to more CodeGen tests to use CHECK-LABEL for labels corresponding to function...

All changes were made by the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    grep -q "^; *RUN: *llc.*debug" $NAME && continue
    grep -q "^; *RUN:.*llvm-objdump" $NAME && continue
    grep -q "^; *RUN: *opt.*" $NAME && continue
    TEMP=`mktemp -t temp`
    cp $NAME $TEMP
    sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
    while read FUNC; do
      sed -i '' "s/;\([A-Za-z0-9_-]*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC[:]* *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
    done
    sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
    sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
    sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
    sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
    mv $TEMP $NAME
  done

This script catches a superset of the cases caught by the script associated with commit r186280. It initially found some false positives due to unusual constructs in a minority of tests; all such cases were disambiguated first in commit r186621.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186624 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/2012-08-30-select.ll b/test/CodeGen/ARM/2012-08-30-select.ll
index 8471be5330b85175e2975f1bf534aca09b37183d..2fd8df4753125141cc55c0c902973cedf132b8f1 100644 (file)
--- a/test/CodeGen/ARM/2012-08-30-select.ll
+++ b/test/CodeGen/ARM/2012-08-30-select.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
 ; rdar://12201387
 
-;CHECK: select_s_v_v
+;CHECK-LABEL: select_s_v_v:
 ;CHECK: it  ne
 ;CHECK-NEXT: vmovne.i32
 ;CHECK: bx

diff --git a/test/CodeGen/ARM/2012-11-14-subs_carry.ll b/test/CodeGen/ARM/2012-11-14-subs_carry.ll
index 38700f3a8d1090edd2dbb1823ad7b98609007502..8df295a2f6580121a1f7d7b03aa8266662048951 100644 (file)
--- a/test/CodeGen/ARM/2012-11-14-subs_carry.ll
+++ b/test/CodeGen/ARM/2012-11-14-subs_carry.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
 
-;CHECK: foo
+;CHECK-LABEL: foo:
 ;CHECK: adds
 ;CHECK-NEXT: adc
 ;CHECK-NEXT: bx

diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll
index a364793deafb0995fdff71f4b080b53589a72d56..854864277720d65315f85ed52be6b1597e645661 100644 (file)
--- a/test/CodeGen/ARM/arm-modifier.ll
+++ b/test/CodeGen/ARM/arm-modifier.ll
@@ -60,7 +60,7 @@ ret void
 
 define i64 @f4(i64* %val) nounwind {
 entry:
-  ;CHECK: f4
+  ;CHECK-LABEL: f4:
   ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
   %0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
   ret i64 %0

diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll
index 13c895c1880d7d505b35c27bed976b89b41de6f6..81a59dbdfe90772fd02d01c978e5418568ed45ac 100644 (file)
--- a/test/CodeGen/ARM/vcge.ll
+++ b/test/CodeGen/ARM/vcge.ll
@@ -187,7 +187,7 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
 ; Floating-point comparisons against zero produce results with integer
 ; elements, not floating-point elements.
 define void @test_vclez_fp() nounwind optsize {
-;CHECK: test_vclez_fp
+;CHECK-LABEL: test_vclez_fp:
 ;CHECK: vcle.f32
 entry:
   %0 = fcmp ole <4 x float> undef, zeroinitializer

diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll
index 8805ef7fb84170566121b9230dec9f276e831edc..b24be2654dfc5945bc5363a5d7fce8c6244c9ce6 100644 (file)
--- a/test/CodeGen/ARM/vdup.ll
+++ b/test/CodeGen/ARM/vdup.ll
@@ -263,7 +263,7 @@ define void @redundantVdup(<8 x i8>* %ptr) nounwind {
 }
 
 define <4 x i32> @tdupi(i32 %x, i32 %y) {
-;CHECK: tdupi
+;CHECK-LABEL: tdupi:
 ;CHECK: vdup.32
   %1 = insertelement <4 x i32> undef, i32 %x, i32 0
   %2 = insertelement <4 x i32> %1, i32 %x, i32 1
@@ -273,7 +273,7 @@ define <4 x i32> @tdupi(i32 %x, i32 %y) {
 }
 
 define <4 x float> @tdupf(float %x, float %y) {
-;CHECK: tdupf
+;CHECK-LABEL: tdupf:
 ;CHECK: vdup.32
   %1 = insertelement <4 x float> undef, float %x, i32 0
   %2 = insertelement <4 x float> %1, float %x, i32 1
@@ -285,7 +285,7 @@ define <4 x float> @tdupf(float %x, float %y) {
 ; This test checks that when splatting an element from a vector into another,
 ; the value isn't moved out to GPRs first.
 define <4 x i32> @tduplane(<4 x i32> %invec) {
-;CHECK: tduplane
+;CHECK-LABEL: tduplane:
 ;CHECK-NOT: vmov {{.*}}, d16[1]
 ;CHECK: vdup.32 {{.*}}, d16[1]
   %in = extractelement <4 x i32> %invec, i32 1

diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll
index a378555eedb387b62170481c40886d5a40e9579d..7a83a4c0cac66ce3aebef6858b435c10f477e224 100644 (file)
--- a/test/CodeGen/ARM/vldlane.ll
+++ b/test/CodeGen/ARM/vldlane.ll
@@ -502,7 +502,7 @@ declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x flo
 ; we don't currently have a QQQQ_VFP2 super-regclass.  (The "0" for the low
 ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
 define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
-;CHECK: test_qqqq_regsequence_subreg
+;CHECK-LABEL: test_qqqq_regsequence_subreg:
 ;CHECK: vld3.16
   %tmp63 = extractvalue [6 x i64] %b, 5
   %tmp64 = zext i64 %tmp63 to i128

diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll
index 2b277a2222df16235801d303d0398813f77ccce3..8b63138bda813e0d95e4848718e76b5c0043fa8a 100644 (file)
--- a/test/CodeGen/ARM/vmov.ll
+++ b/test/CodeGen/ARM/vmov.ll
@@ -386,7 +386,7 @@ entry:
 ; rdar://10723651
 define void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {
 entry:
-;CHECK: any_extend
+;CHECK-LABEL: any_extend:
 ;CHECK: vmovl
   %and.i186 = zext <4 x i1> %x to <4 x i32>
   %add.i185 = sub <4 x i32> %and.i186, %y

diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll
index af8246325c340f3b7c9c2dc76101b0a772f685e1..7551a562cf0eaa93db71d922ed270a016887515d 100644 (file)
--- a/test/CodeGen/ARM/vst2.ll
+++ b/test/CodeGen/ARM/vst2.ll
@@ -111,7 +111,7 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
 }
 
 define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
-;CHECK: vst2update
+;CHECK-LABEL: vst2update:
 ;CHECK: vst2.16 {d16, d17}, [r0]!
        %tmp1 = load <4 x i16>* %B
        tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
@@ -120,7 +120,7 @@ define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
 }
 
 define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 {
-;CHECK: vst2update2
+;CHECK-LABEL: vst2update2:
 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]!
   %tmp1 = load <4 x float>* %this
   call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind

diff --git a/test/CodeGen/SPARC/2011-01-11-CC.ll b/test/CodeGen/SPARC/2011-01-11-CC.ll
index 599b451993e2d06bdece5b081d8df7a2c6169107..edbcb4929ff0cd3997b4c5f99e69173543352b70 100644 (file)
--- a/test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/test/CodeGen/SPARC/2011-01-11-CC.ll
@@ -63,10 +63,10 @@ entry:
 
 define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
 entry:
-;V8: test_select_int_fcc
+;V8-LABEL: test_select_int_fcc:
 ;V8: fcmps
 ;V8: {{fbe|fbne}}
-;V9: test_select_int_fcc
+;V9-LABEL: test_select_int_fcc:
 ;V9: fcmps
 ;V9-NOT: {{fbe|fbne}}
 ;V9: mov{{e|ne}} %fcc0
@@ -78,10 +78,10 @@ entry:
 
 define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
 entry:
-;V8: test_select_fp_fcc
+;V8-LABEL: test_select_fp_fcc:
 ;V8: fcmps
 ;V8: {{fbe|fbne}}
-;V9: test_select_fp_fcc
+;V9-LABEL: test_select_fp_fcc:
 ;V9: fcmps
 ;V9-NOT: {{fbe|fbne}}
 ;V9: fmovs{{e|ne}} %fcc0
@@ -92,10 +92,10 @@ entry:
 
 define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
 entry:
-;V8: test_select_dfp_fcc
+;V8-LABEL: test_select_dfp_fcc:
 ;V8: fcmpd
 ;V8: {{fbne|fbe}}
-;V9: test_select_dfp_fcc
+;V9-LABEL: test_select_dfp_fcc:
 ;V9: fcmpd
 ;V9-NOT: {{fbne|fbe}}
 ;V9: fmovd{{e|ne}} %fcc0

diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
index 5fd5687ba5b6fbe91c4b295eda358c39e552646a..7cc7868e44f939bccef56a5a5f329d11971cd848 100644 (file)
--- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
+++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
@@ -6,12 +6,12 @@
 
 define i8* @frameaddr() nounwind readnone {
 entry:
-;V8: frameaddr
+;V8-LABEL: frameaddr:
 ;V8: save %sp, -96, %sp
 ;V8: jmp %i7+8
 ;V8: restore %g0, %fp, %o0
 
-;V9: frameaddr
+;V9-LABEL: frameaddr:
 ;V9: save %sp, -96, %sp
 ;V9: jmp %i7+8
 ;V9: restore %g0, %fp, %o0
@@ -21,13 +21,13 @@ entry:
 
 define i8* @frameaddr2() nounwind readnone {
 entry:
-;V8: frameaddr2
+;V8-LABEL: frameaddr2:
 ;V8: ta 3
 ;V8: ld [%fp+56], {{.+}}
 ;V8: ld [{{.+}}+56], {{.+}}
 ;V8: ld [{{.+}}+56], {{.+}}
 
-;V9: frameaddr2
+;V9-LABEL: frameaddr2:
 ;V9: flushw
 ;V9: ld [%fp+56], {{.+}}
 ;V9: ld [{{.+}}+56], {{.+}}
@@ -42,10 +42,10 @@ declare i8* @llvm.frameaddress(i32) nounwind readnone
 
 define i8* @retaddr() nounwind readnone {
 entry:
-;V8: retaddr
+;V8-LABEL: retaddr:
 ;V8: or %g0, %o7, {{.+}}
 
-;V9: retaddr
+;V9-LABEL: retaddr:
 ;V9: or %g0, %o7, {{.+}}
 
   %0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -54,25 +54,25 @@ entry:
 
 define i8* @retaddr2() nounwind readnone {
 entry:
-;V8: retaddr2
+;V8-LABEL: retaddr2:
 ;V8: ta 3
 ;V8: ld [%fp+56], {{.+}}
 ;V8: ld [{{.+}}+56], {{.+}}
 ;V8: ld [{{.+}}+60], {{.+}}
 
-;V9: retaddr2
+;V9-LABEL: retaddr2:
 ;V9: flushw
 ;V9: ld [%fp+56], {{.+}}
 ;V9: ld [{{.+}}+56], {{.+}}
 ;V9: ld [{{.+}}+60], {{.+}}
 
-;V8LEAF: retaddr2
+;V8LEAF-LABEL: retaddr2:
 ;V8LEAF: ta 3
 ;V8LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
 ;V8LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
 ;V8LEAF: ld [%[[R1]]+60], {{.+}}
 
-;V9LEAF: retaddr2
+;V9LEAF-LABEL: retaddr2:
 ;V9LEAF: flushw
 ;V9LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
 ;V9LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]

diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index 401d902cc0ee6e23ba074da851faf08adf708269..c71e7c00b9165b5ce480a7e2a45ad555500b2676 100644 (file)
--- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -54,7 +54,7 @@ bb5:                                              ; preds = %bb, %entry
 
 define i32 @test_inlineasm(i32 %a) nounwind {
 entry:
-;CHECK:      test_inlineasm
+;CHECK-LABEL:      test_inlineasm:
 ;CHECK:      sethi
 ;CHECK:      !NO_APP
 ;CHECK-NEXT: cmp
@@ -80,7 +80,7 @@ declare i32 @bar(i32)
 
 define i32 @test_implicit_def() nounwind {
 entry:
-;UNOPT:       test_implicit_def
+;UNOPT-LABEL:       test_implicit_def:
 ;UNOPT:       call func
 ;UNOPT-NEXT:  nop
   %0 = tail call i32 @func(i32* undef) nounwind
@@ -89,7 +89,7 @@ entry:
 
 define i32 @prevent_o7_in_call_delay_slot(i32 %i0) {
 entry:
-;CHECK:       prevent_o7_in_call_delay_slot
+;CHECK-LABEL:       prevent_o7_in_call_delay_slot:
 ;CHECK:       add %i0, 2, %o5
 ;CHECK:       add %i0, 3, %o7
 ;CHECK:       add %o5, %o7, %o0
@@ -150,7 +150,7 @@ entry:
 
 define i32 @restore_sethi(i32 %a) {
 entry:
-;CHECK: restore_sethi
+;CHECK-LABEL: restore_sethi:
 ;CHECK-NOT: sethi  3
 ;CHECK: restore %g0, 3072, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -161,7 +161,7 @@ entry:
 
 define i32 @restore_sethi_3bit(i32 %a) {
 entry:
-;CHECK: restore_sethi_3bit
+;CHECK-LABEL: restore_sethi_3bit:
 ;CHECK: sethi  6
 ;CHECK-NOT: restore %g0, 6144, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -172,7 +172,7 @@ entry:
 
 define i32 @restore_sethi_large(i32 %a) {
 entry:
-;CHECK: restore_sethi_large
+;CHECK-LABEL: restore_sethi_large:
 ;CHECK: sethi  4000, %i0
 ;CHECK: restore %g0, %g0, %g0
   %0 = tail call i32 @bar(i32 %a) nounwind

diff --git a/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
index 85c16e4684edd3876861984a6e1543423079fbe5..408b13d70a38f8cc0b8531ac4011c554919d3581 100644 (file)
--- a/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
+++ b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
@@ -6,7 +6,7 @@
 
 define i32 @test() nounwind {
 entry:
-;CHECK:     test
+;CHECK-LABEL:     test:
 ;CHECK:     st
 ;CHECK:     st
 ;CHECK:     st

diff --git a/test/CodeGen/SPARC/2011-01-22-SRet.ll b/test/CodeGen/SPARC/2011-01-22-SRet.ll
index c6a1dc9eba65852c2b60635fd9607e06752bc2e4..fc44bc495f4624209802f87694cbefea8bfde925 100644 (file)
--- a/test/CodeGen/SPARC/2011-01-22-SRet.ll
+++ b/test/CodeGen/SPARC/2011-01-22-SRet.ll
@@ -4,7 +4,7 @@
 
 define weak void @make_foo(%struct.foo_t* noalias sret %agg.result, i32 %a, i32 %b, i32 %c) nounwind {
 entry:
-;CHECK: make_foo
+;CHECK-LABEL: make_foo:
 ;CHECK: ld [%sp+64], {{.+}}
 ;CHECK: jmp %o7+12
   %0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0
@@ -18,7 +18,7 @@ entry:
 
 define i32 @test() nounwind {
 entry:
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK: st {{.+}}, [%sp+64]
 ;CHECK: call make_foo
 ;CHECK: unimp 12

diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll
index 077be12faa92dd0c355ca6cb723139eb8a988ef3..148bafec4014f72a5fd98da0b349c19d655ae09b 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-mov.ll
+++ b/test/CodeGen/Thumb2/thumb2-mov.ll
@@ -259,7 +259,7 @@ define i32 @f5(i32 %a) {
 }
 
 define i32 @f6(i32 %a) {
-;CHECK: f6
+;CHECK-LABEL: f6:
 ;CHECK: movw    r0, #65535
     %tmp = add i32 0, 65535
     ret i32 %tmp

diff --git a/test/CodeGen/X86/2011-04-19-sclr-bb.ll b/test/CodeGen/X86/2011-04-19-sclr-bb.ll
index 771e4b3a081595990142dd03bacbcb5f8352240f..b77cc40acf3c8a76876a9129f5b97bd8643ba147 100644 (file)
--- a/test/CodeGen/X86/2011-04-19-sclr-bb.ll
+++ b/test/CodeGen/X86/2011-04-19-sclr-bb.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
 
 ; Make sure that values of illegal types are not scalarized between basic blocks.
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK-NOT: pinsrw
 ;CHECK-NOT: pextrb
 ;CHECK: ret

diff --git a/test/CodeGen/X86/2011-05-09-loaduse.ll b/test/CodeGen/X86/2011-05-09-loaduse.ll
index 8673d7433fac09e12ec634e39f28cd0b60abdac5..adcea5cf61592147485ce63e6f43319f180f412c 100644 (file)
--- a/test/CodeGen/X86/2011-05-09-loaduse.ll
+++ b/test/CodeGen/X86/2011-05-09-loaduse.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
 
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK-not: pshufd
 ;CHECK: ret
 define float @test(<4 x float>* %A) nounwind {

diff --git a/test/CodeGen/X86/2011-10-27-tstore.ll b/test/CodeGen/X86/2011-10-27-tstore.ll
index 6e83f6713ae45c83c458e20134ca8810306b4511..6dea92b63071551a9d20d5b5c94eefbea2b95f1f 100644 (file)
--- a/test/CodeGen/X86/2011-10-27-tstore.ll
+++ b/test/CodeGen/X86/2011-10-27-tstore.ll
@@ -2,7 +2,7 @@
 
 target triple = "x86_64-unknown-linux-gnu"
 
-;CHECK: ltstore
+;CHECK-LABEL: ltstore:
 ;CHECK: movq
 ;CHECK: movq
 ;CHECK: ret

diff --git a/test/CodeGen/X86/2011-10-30-padd.ll b/test/CodeGen/X86/2011-10-30-padd.ll
index 180ca15a0ee2040c94a1e379518d35c3a250ac65..1b8c12bc8e38145323e44d08a4941213a7cf8a37 100644 (file)
--- a/test/CodeGen/X86/2011-10-30-padd.ll
+++ b/test/CodeGen/X86/2011-10-30-padd.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
 
-;CHECK: addXX_test
+;CHECK-LABEL: addXX_test:
 ;CHECK: padd
 ;CHECK: ret
 
@@ -10,7 +10,7 @@ define <16 x i8> @addXX_test(<16 x i8> %a) {
       ret <16 x i8> %b
 }
 
-;CHECK: instcombine_test
+;CHECK-LABEL: instcombine_test:
 ;CHECK: padd
 ;CHECK: ret
 define <16 x i8> @instcombine_test(<16 x i8> %a) {

diff --git a/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll b/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
index 75efcf5ac47bb312e4b9643b28442448407c640b..78cdfcf0e1f0e73a7f67dc9f38480a09397fb097 100644 (file)
--- a/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
+++ b/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ; 0x1 means that we only look at the first bit.
 
 ;CHECK: 0x1
-;CHECK: ui_to_fp_conv
+;CHECK-LABEL: ui_to_fp_conv:
 ;CHECK: ret
 define void @ui_to_fp_conv(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) nounwind {
 allocas:

diff --git a/test/CodeGen/X86/2012-01-11-split-cv.ll b/test/CodeGen/X86/2012-01-11-split-cv.ll
index 7e914984fe445431ae388720a1210a667c9c57b1..69d4b93bb78deda7734c233643f6eef88c67b6ea 100644 (file)
--- a/test/CodeGen/X86/2012-01-11-split-cv.ll
+++ b/test/CodeGen/X86/2012-01-11-split-cv.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7-avx -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
 
-;CHECK: add18i16
+;CHECK-LABEL: add18i16:
 define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind {
 ;CHECK: vmovaps
   %b = load <18 x i16>* %bp, align 16

diff --git a/test/CodeGen/X86/2012-01-18-vbitcast.ll b/test/CodeGen/X86/2012-01-18-vbitcast.ll
index 3ce7db6e41383dd6f504ac02b9e835535501b213..9eb59e41ef7de29486a8cd3795dadc9f4d8b956a 100644 (file)
--- a/test/CodeGen/X86/2012-01-18-vbitcast.ll
+++ b/test/CodeGen/X86/2012-01-18-vbitcast.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win32 | FileCheck %s
 
-;CHECK: vcast
+;CHECK-LABEL: vcast:
 define <2 x i32> @vcast(<2 x float> %a, <2 x float> %b) {
 ;CHECK: pmovzxdq
 ;CHECK: pmovzxdq

diff --git a/test/CodeGen/X86/2012-07-10-extload64.ll b/test/CodeGen/X86/2012-07-10-extload64.ll
index 4abdded38d8ccd45936e0c17a706c677593eef29..723302723b6ba6cc779b1bdf069e17086f5018cd 100644 (file)
--- a/test/CodeGen/X86/2012-07-10-extload64.ll
+++ b/test/CodeGen/X86/2012-07-10-extload64.ll
@@ -13,7 +13,7 @@ entry:
 }
 
 ; Make sure that we store a 64bit value, even on 32bit systems.
-;CHECK: store_64
+;CHECK-LABEL: store_64:
 define void @store_64(<2 x i32>* %ptr) {
 BB:
   store <2 x i32> zeroinitializer, <2 x i32>* %ptr
@@ -22,7 +22,7 @@ BB:
 ;CHECK: ret
 }
 
-;CHECK: load_64
+;CHECK-LABEL: load_64:
 define <2 x i32> @load_64(<2 x i32>* %ptr) {
 BB:
   %t = load <2 x i32>* %ptr

diff --git a/test/CodeGen/X86/2012-07-15-broadcastfold.ll b/test/CodeGen/X86/2012-07-15-broadcastfold.ll
index 2c7dfc8dfd452d46b192a0cef9b53711289217c3..1c39c747cdc8d07c113476aae659f9ed88113d5c 100644 (file)
--- a/test/CodeGen/X86/2012-07-15-broadcastfold.ll
+++ b/test/CodeGen/X86/2012-07-15-broadcastfold.ll
@@ -2,7 +2,7 @@
 
 declare x86_fastcallcc i64 @barrier()
 
-;CHECK: bcast_fold
+;CHECK-LABEL: bcast_fold:
 ;CHECK: vmov{{[au]}}ps %xmm{{[0-9]+}}, [[SPILLED:[^\)]+\)]]
 ;CHECK: barrier
 ;CHECK: vbroadcastss [[SPILLED]], %ymm0

diff --git a/test/CodeGen/X86/2012-1-10-buildvector.ll b/test/CodeGen/X86/2012-1-10-buildvector.ll
index ff6be369dc57176ff2087735ed3ba2cdd9f6cf5c..a5f64c5eaf552fce33de94eb01130228b23c7c70 100644 (file)
--- a/test/CodeGen/X86/2012-1-10-buildvector.ll
+++ b/test/CodeGen/X86/2012-1-10-buildvector.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
 target triple = "i686-pc-win32"
 
-;CHECK: bad_cast
+;CHECK-LABEL: bad_cast:
 define void @bad_cast() {
 entry:
   %vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
@@ -14,7 +14,7 @@ entry:
 }
 
 
-;CHECK: bad_insert
+;CHECK-LABEL: bad_insert:
 define void @bad_insert(i32 %t) {
 entry:
 ;CHECK: vpinsrd

diff --git a/test/CodeGen/X86/MergeConsecutiveStores.ll b/test/CodeGen/X86/MergeConsecutiveStores.ll
index bb227a0185dfabcda126d27ad422c33515031e63..0ef3aa5b6f073cfb33ba816b6e441d021fae1ab6 100644 (file)
--- a/test/CodeGen/X86/MergeConsecutiveStores.ll
+++ b/test/CodeGen/X86/MergeConsecutiveStores.ll
@@ -147,7 +147,7 @@ define void @merge_nonconst_store(i32 %count, i8 %zz, %struct.A* nocapture %p) n
 }
 
 
-;CHECK: merge_loads_i16
+;CHECK-LABEL: merge_loads_i16:
 ; load:
 ;CHECK: movw
 ; store:
@@ -181,7 +181,7 @@ define void @merge_loads_i16(i32 %count, %struct.A* noalias nocapture %q, %struc
 }
 
 ; The loads and the stores are interleved. Can't merge them.
-;CHECK: no_merge_loads
+;CHECK-LABEL: no_merge_loads:
 ;CHECK: movb
 ;CHECK: movb
 ;CHECK: movb
@@ -215,7 +215,7 @@ a4:                                       ; preds = %4, %.lr.ph
 }
 
 
-;CHECK: merge_loads_integer
+;CHECK-LABEL: merge_loads_integer:
 ; load:
 ;CHECK: movq
 ; store:
@@ -249,7 +249,7 @@ define void @merge_loads_integer(i32 %count, %struct.B* noalias nocapture %q, %s
 }
 
 
-;CHECK: merge_loads_vector
+;CHECK-LABEL: merge_loads_vector:
 ; load:
 ;CHECK: movups
 ; store:
@@ -290,7 +290,7 @@ block4:                                       ; preds = %4, %.lr.ph
   ret void
 }
 
-;CHECK: merge_loads_no_align
+;CHECK-LABEL: merge_loads_no_align:
 ; load:
 ;CHECK: movl
 ;CHECK: movl

diff --git a/test/CodeGen/X86/StackColoring.ll b/test/CodeGen/X86/StackColoring.ll
index 6c0f00d17d5acaa19a0cdebf09d09192079e25d3..d0dba42bfa97018d1361a05a192c0c82233025dc 100644 (file)
--- a/test/CodeGen/X86/StackColoring.ll
+++ b/test/CodeGen/X86/StackColoring.ll
@@ -297,8 +297,8 @@ bb3:
 }
 
 
-;YESCOLOR: multi_region_bb
-;NOCOLOR: multi_region_bb
+;YESCOLOR-LABEL: multi_region_bb:
+;NOCOLOR-LABEL: multi_region_bb:
 define void @multi_region_bb() nounwind ssp {
 entry:
   %A.i1 = alloca [100 x i32], align 4
@@ -353,9 +353,9 @@ bb3:
 
 ; Regression test for PR15707.  %buf1 and %buf2 should not be merged
 ; in this test case.
-;YESCOLOR: myCall_pr15707
+;YESCOLOR-LABEL: myCall_pr15707:
 ;YESCOLOR: subq $200008, %rsp
-;NOCOLOR: myCall_pr15707
+;NOCOLOR-LABEL: myCall_pr15707:
 ;NOCOLOR: subq $200008, %rsp
 define void @myCall_pr15707() {
   %buf1 = alloca i8, i32 100000, align 16
@@ -374,8 +374,8 @@ define void @myCall_pr15707() {
 
 ; Check that we don't assert and crash even when there are allocas
 ; outside the declared lifetime regions.
-;YESCOLOR: bad_range
-;NOCOLOR:  bad_range
+;YESCOLOR-LABEL: bad_range:
+;NOCOLOR-LABEL:  bad_range:
 define void @bad_range() nounwind ssp {
 entry:
   %A.i1 = alloca [100 x i32], align 4
@@ -400,8 +400,8 @@ block2:
 
 ; Check that we don't assert and crash even when there are usages
 ; of allocas which do not read or write outside the declared lifetime regions.
-;YESCOLOR: shady_range
-;NOCOLOR:  shady_range
+;YESCOLOR-LABEL: shady_range:
+;NOCOLOR-LABEL:  shady_range:
 
 %struct.Klass = type { i32, i32 }
 

diff --git a/test/CodeGen/X86/WidenArith.ll b/test/CodeGen/X86/WidenArith.ll
index 0383bd665b0fd7d0d8460ee2819d686d5c0fd952..f87b3821dde8854b91d9953f14250feb102134f1 100644 (file)
--- a/test/CodeGen/X86/WidenArith.ll
+++ b/test/CodeGen/X86/WidenArith.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
 
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK: vaddps
 ;CHECK: vmulps
 ;CHECK: vsubps

diff --git a/test/CodeGen/X86/atom-call-reg-indirect.ll b/test/CodeGen/X86/atom-call-reg-indirect.ll
index 632781130d06fb8ac97ceae03f0bf8b75285dcce..933b98b82c1bcdab7af656850a68f16b36917443 100644 (file)
--- a/test/CodeGen/X86/atom-call-reg-indirect.ll
+++ b/test/CodeGen/X86/atom-call-reg-indirect.ll
@@ -8,7 +8,7 @@
 %class.A = type { i32 (...)** }
 
 define i32 @test1() #0 {
-  ;ATOM: test1
+  ;ATOM-LABEL: test1:
 entry:
   %call = tail call %class.A* @_Z3facv()
   %0 = bitcast %class.A* %call to void (%class.A*)***
@@ -30,7 +30,7 @@ declare %class.A* @_Z3facv() #1
 @p = external global void (i32)**
 
 define i32 @test2() #0 {
-  ;ATOM: test2
+  ;ATOM-LABEL: test2:
 entry:
   %0 = load void (i32)*** @p, align 8
   %1 = load void (i32)** %0, align 8

diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll
index 224cc50b076a6416f65ff4ed4f55006065c24f97..a98e0761ce3131c5f075176e3801fc0411c46554 100644 (file)
--- a/test/CodeGen/X86/avx-blend.ll
+++ b/test/CodeGen/X86/avx-blend.ll
@@ -2,7 +2,7 @@
 
 ; AVX128 tests:
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
@@ -11,7 +11,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
 }
 
 
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i32:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
@@ -20,7 +20,7 @@ define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
 }
 
 
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
@@ -29,7 +29,7 @@ define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
 }
 
 
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i64:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
@@ -38,7 +38,7 @@ define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
 }
 
 
-;CHECK: vsel_i8
+;CHECK-LABEL: vsel_i8:
 ;CHECK: vpblendvb
 ;CHECK: ret
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
@@ -50,7 +50,7 @@ define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
 ; AVX256 tests:
 
 
-;CHECK: vsel_float8
+;CHECK-LABEL: vsel_float8:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
@@ -58,7 +58,7 @@ define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
   ret <8 x float> %vsel
 }
 
-;CHECK: vsel_i328
+;CHECK-LABEL: vsel_i328:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
@@ -66,7 +66,7 @@ define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
   ret <8 x i32> %vsel
 }
 
-;CHECK: vsel_double8
+;CHECK-LABEL: vsel_double8:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
@@ -74,7 +74,7 @@ define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
   ret <8 x double> %vsel
 }
 
-;CHECK: vsel_i648
+;CHECK-LABEL: vsel_i648:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {

diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll
index 655902a8f58e0b8df88f03f35a92c10effa5e8e5..a625601961e8ef0e68518c3276c8e6368328e247 100644 (file)
--- a/test/CodeGen/X86/avx-shuffle.ll
+++ b/test/CodeGen/X86/avx-shuffle.ll
@@ -220,7 +220,7 @@ define <16 x i16> @narrow(<16 x i16> %a) nounwind alwaysinline {
   ret <16 x i16> %t
 }
 
-;CHECK: test17
+;CHECK-LABEL: test17:
 ;CHECK-NOT: vinsertf128
 ;CHECK: ret
 define   <8 x float> @test17(<4 x float> %y) {

diff --git a/test/CodeGen/X86/avx-zext.ll b/test/CodeGen/X86/avx-zext.ll
index 582537ea906f7e893e8bbf8e7e4189ea67dc5932..e2b6c552da9f7187ca6c2abca6173e285364c8a6 100644 (file)
--- a/test/CodeGen/X86/avx-zext.ll
+++ b/test/CodeGen/X86/avx-zext.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 
 define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
-;CHECK: zext_8i16_to_8i32
+;CHECK-LABEL: zext_8i16_to_8i32:
 ;CHECK: vpunpckhwd
 ;CHECK: ret
 
@@ -10,7 +10,7 @@ define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp
 }
 
 define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
-;CHECK: zext_4i32_to_4i64
+;CHECK-LABEL: zext_4i32_to_4i64:
 ;CHECK: vpunpckhdq
 ;CHECK: ret
 
@@ -19,7 +19,7 @@ define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp
 }
 
 define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
-;CHECK: zext_8i8_to_8i32
+;CHECK-LABEL: zext_8i8_to_8i32:
 ;CHECK: vpunpckhwd
 ;CHECK: vpmovzxwd
 ;CHECK: vinsertf128

diff --git a/test/CodeGen/X86/avx2-vbroadcast.ll b/test/CodeGen/X86/avx2-vbroadcast.ll
index b804233663d47ce121bd67633f0ed1e62842e3e5..5610416d39a36ed8b708254b9d28cc301204d37a 100644 (file)
--- a/test/CodeGen/X86/avx2-vbroadcast.ll
+++ b/test/CodeGen/X86/avx2-vbroadcast.ll
@@ -259,7 +259,7 @@ define <4 x double> @_inreg3(double %scalar) nounwind uwtable readnone ssp {
   ret <4 x double> %wide
 }
 
-;CHECK: _inreg8xfloat
+;CHECK-LABEL: _inreg8xfloat:
 ;CHECK: vbroadcastss
 ;CHECK: ret
 define   <8 x float> @_inreg8xfloat(<8 x float> %a) {
@@ -267,7 +267,7 @@ define   <8 x float> @_inreg8xfloat(<8 x float> %a) {
   ret <8 x float> %b
 }
 
-;CHECK: _inreg4xfloat
+;CHECK-LABEL: _inreg4xfloat:
 ;CHECK: vbroadcastss
 ;CHECK: ret
 define   <4 x float> @_inreg4xfloat(<4 x float> %a) {
@@ -275,7 +275,7 @@ define   <4 x float> @_inreg4xfloat(<4 x float> %a) {
   ret <4 x float> %b
 }
 
-;CHECK: _inreg16xi16
+;CHECK-LABEL: _inreg16xi16:
 ;CHECK: vpbroadcastw
 ;CHECK: ret
 define   <16 x i16> @_inreg16xi16(<16 x i16> %a) {
@@ -283,7 +283,7 @@ define   <16 x i16> @_inreg16xi16(<16 x i16> %a) {
   ret <16 x i16> %b
 }
 
-;CHECK: _inreg8xi16
+;CHECK-LABEL: _inreg8xi16:
 ;CHECK: vpbroadcastw
 ;CHECK: ret
 define   <8 x i16> @_inreg8xi16(<8 x i16> %a) {
@@ -292,7 +292,7 @@ define   <8 x i16> @_inreg8xi16(<8 x i16> %a) {
 }
 
 
-;CHECK: _inreg4xi64
+;CHECK-LABEL: _inreg4xi64:
 ;CHECK: vpbroadcastq
 ;CHECK: ret
 define   <4 x i64> @_inreg4xi64(<4 x i64> %a) {
@@ -300,7 +300,7 @@ define   <4 x i64> @_inreg4xi64(<4 x i64> %a) {
   ret <4 x i64> %b
 }
 
-;CHECK: _inreg2xi64
+;CHECK-LABEL: _inreg2xi64:
 ;CHECK: vpbroadcastq
 ;CHECK: ret
 define   <2 x i64> @_inreg2xi64(<2 x i64> %a) {
@@ -308,7 +308,7 @@ define   <2 x i64> @_inreg2xi64(<2 x i64> %a) {
   ret <2 x i64> %b
 }
 
-;CHECK: _inreg4xdouble
+;CHECK-LABEL: _inreg4xdouble:
 ;CHECK: vbroadcastsd
 ;CHECK: ret
 define   <4 x double> @_inreg4xdouble(<4 x double> %a) {
@@ -316,7 +316,7 @@ define   <4 x double> @_inreg4xdouble(<4 x double> %a) {
   ret <4 x double> %b
 }
 
-;CHECK: _inreg2xdouble
+;CHECK-LABEL: _inreg2xdouble:
 ;CHECK: vpbroadcastq
 ;CHECK: ret
 define   <2 x double> @_inreg2xdouble(<2 x double> %a) {
@@ -324,7 +324,7 @@ define   <2 x double> @_inreg2xdouble(<2 x double> %a) {
   ret <2 x double> %b
 }
 
-;CHECK: _inreg8xi32
+;CHECK-LABEL: _inreg8xi32:
 ;CHECK: vpbroadcastd
 ;CHECK: ret
 define   <8 x i32> @_inreg8xi32(<8 x i32> %a) {
@@ -332,7 +332,7 @@ define   <8 x i32> @_inreg8xi32(<8 x i32> %a) {
   ret <8 x i32> %b
 }
 
-;CHECK: _inreg4xi32
+;CHECK-LABEL: _inreg4xi32:
 ;CHECK: vpbroadcastd
 ;CHECK: ret
 define   <4 x i32> @_inreg4xi32(<4 x i32> %a) {
@@ -340,7 +340,7 @@ define   <4 x i32> @_inreg4xi32(<4 x i32> %a) {
   ret <4 x i32> %b
 }
 
-;CHECK: _inreg32xi8
+;CHECK-LABEL: _inreg32xi8:
 ;CHECK: vpbroadcastb
 ;CHECK: ret
 define   <32 x i8> @_inreg32xi8(<32 x i8> %a) {
@@ -348,7 +348,7 @@ define   <32 x i8> @_inreg32xi8(<32 x i8> %a) {
   ret <32 x i8> %b
 }
 
-;CHECK: _inreg16xi8
+;CHECK-LABEL: _inreg16xi8:
 ;CHECK: vpbroadcastb
 ;CHECK: ret
 define   <16 x i8> @_inreg16xi8(<16 x i8> %a) {

diff --git a/test/CodeGen/X86/blend-msb.ll b/test/CodeGen/X86/blend-msb.ll
index e565da74a082e537d28d986c147b9f33b00bf227..fa775bd0b914e33b5c2ceb70378c49f53f251500 100644 (file)
--- a/test/CodeGen/X86/blend-msb.ll
+++ b/test/CodeGen/X86/blend-msb.ll
@@ -4,7 +4,7 @@
 ; In this test we check that sign-extend of the mask bit is performed by
 ; shifting the needed bit to the MSB, and not using shl+sra.
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
 ;CHECK: movl $-2147483648
 ;CHECK-NEXT: movd
 ;CHECK-NEXT: blendvps
@@ -14,7 +14,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
   ret <4 x float> %vsel
 }
 
-;CHECK: vsel_4xi8
+;CHECK-LABEL: vsel_4xi8:
 ;CHECK: movl $-2147483648
 ;CHECK-NEXT: movd
 ;CHECK-NEXT: blendvps
@@ -28,7 +28,7 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
 ; We do not have native support for v8i16 blends and we have to use the
 ; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not r
 ; reduce the mask in this case.
-;CHECK: vsel_8xi16
+;CHECK-LABEL: vsel_8xi16:
 ;CHECK: psllw
 ;CHECK: psraw
 ;CHECK: pblendvb

diff --git a/test/CodeGen/X86/chain_order.ll b/test/CodeGen/X86/chain_order.ll
index 056fd2741fa04822c6254cd1ef186515e2ce49c4..8c1c86420f6bcc699f6dcfcdc766e5cc11fba1e5 100644 (file)
--- a/test/CodeGen/X86/chain_order.ll
+++ b/test/CodeGen/X86/chain_order.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mcpu=corei7-avx -mtriple=x86_64-linux | FileCheck %s
 
-;CHECK: cftx020
+;CHECK-LABEL: cftx020:
 ;CHECK: vmovsd  (%rdi), %xmm{{.*}}
 ;CHECK: vmovsd  16(%rdi), %xmm{{.*}}
 ;CHECK: vmovhpd  8(%rdi), %xmm{{.*}}

diff --git a/test/CodeGen/X86/code_placement_align_all.ll b/test/CodeGen/X86/code_placement_align_all.ll
index 1e5e8f780b70877410c55962a6860ed9bf86aed2..53df90620204e13b116e4d8c2f40a49aae18cd05 100644 (file)
--- a/test/CodeGen/X86/code_placement_align_all.ll
+++ b/test/CodeGen/X86/code_placement_align_all.ll
@@ -1,6 +1,6 @@
 ; RUN: llc  -mcpu=corei7 -mtriple=x86_64-linux -align-all-blocks=16 < %s | FileCheck %s
 
-;CHECK: foo
+;CHECK-LABEL: foo:
 ;CHECK: .align  65536, 0x90
 ;CHECK: .align  65536, 0x90
 ;CHECK: .align  65536, 0x90

diff --git a/test/CodeGen/X86/pmovext.ll b/test/CodeGen/X86/pmovext.ll
index 16e9c28fcdefede81d7646fc94f090e12069d616..b85b4c39ea8eeacf26b5d866f7bbc7a85cb9b4ef 100644 (file)
--- a/test/CodeGen/X86/pmovext.ll
+++ b/test/CodeGen/X86/pmovext.ll
@@ -2,7 +2,7 @@
 
 ; rdar://11897677
 
-;CHECK: intrin_pmov
+;CHECK-LABEL: intrin_pmov:
 ;CHECK: pmovzxbw  (%{{.*}}), %xmm0
 ;CHECK-NEXT: movdqu
 ;CHECK-NEXT: ret

diff --git a/test/CodeGen/X86/sandybridge-loads.ll b/test/CodeGen/X86/sandybridge-loads.ll
index 5a23cf136d852574a4fa40fe32800b400b6be3c7..b8c364e2961c75951ecb76545c68762cb405507e 100644 (file)
--- a/test/CodeGen/X86/sandybridge-loads.ll
+++ b/test/CodeGen/X86/sandybridge-loads.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
 
-;CHECK: wideloads
+;CHECK-LABEL: wideloads:
 ;CHECK: vmovaps
 ;CHECK: vinsertf128
 ;CHECK: vmovaps

diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll
index a2a0debf9e95731a2a68204254c658b99af2a62e..bd92d22d5e738222b1bf2c0049f67eaca3b5963c 100644 (file)
--- a/test/CodeGen/X86/sse41-blend.ll
+++ b/test/CodeGen/X86/sse41-blend.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse41 | FileCheck %s
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
@@ -9,7 +9,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
 }
 
 
-;CHECK: vsel_4xi8
+;CHECK-LABEL: vsel_4xi8:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
@@ -17,7 +17,7 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
   ret <4 x i8> %vsel
 }
 
-;CHECK: vsel_4xi16
+;CHECK-LABEL: vsel_4xi16:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
@@ -26,7 +26,7 @@ define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
 }
 
 
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i32:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
@@ -35,7 +35,7 @@ define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
 }
 
 
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double:
 ;CHECK: blendvpd
 ;CHECK: ret
 define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
@@ -44,7 +44,7 @@ define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
 }
 
 
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i64:
 ;CHECK: blendvpd
 ;CHECK: ret
 define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
@@ -53,7 +53,7 @@ define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
 }
 
 
-;CHECK: vsel_i8
+;CHECK-LABEL: vsel_i8:
 ;CHECK: pblendvb
 ;CHECK: ret
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {

diff --git a/test/CodeGen/X86/trunc-ext-ld-st.ll b/test/CodeGen/X86/trunc-ext-ld-st.ll
index 1d22a185def383faddc77be7e57a584e2987a956..408bdc81610dae9c724cfcb6995e23723443775c 100644 (file)
--- a/test/CodeGen/X86/trunc-ext-ld-st.ll
+++ b/test/CodeGen/X86/trunc-ext-ld-st.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse41 | FileCheck %s
 
-;CHECK: load_2_i8
+;CHECK-LABEL: load_2_i8:
 ; A single 16-bit load
 ;CHECK: pmovzxbq
 ;CHECK: paddq
@@ -16,7 +16,7 @@ define void @load_2_i8(<2 x i8>* %A)  {
    ret void
 } 
 
-;CHECK: load_2_i16
+;CHECK-LABEL: load_2_i16:
 ; Read 32-bits
 ;CHECK: pmovzxwq
 ;CHECK: paddq
@@ -30,7 +30,7 @@ define void @load_2_i16(<2 x i16>* %A)  {
    ret void
 } 
 
-;CHECK: load_2_i32
+;CHECK-LABEL: load_2_i32:
 ;CHECK: pmovzxdq
 ;CHECK: paddq
 ;CHECK: pshufd
@@ -42,7 +42,7 @@ define void @load_2_i32(<2 x i32>* %A)  {
    ret void
 } 
 
-;CHECK: load_4_i8
+;CHECK-LABEL: load_4_i8:
 ;CHECK: pmovzxbd
 ;CHECK: paddd
 ;CHECK: pshufb
@@ -54,7 +54,7 @@ define void @load_4_i8(<4 x i8>* %A)  {
    ret void
 } 
 
-;CHECK: load_4_i16
+;CHECK-LABEL: load_4_i16:
 ;CHECK: pmovzxwd
 ;CHECK: paddd
 ;CHECK: pshufb
@@ -66,7 +66,7 @@ define void @load_4_i16(<4 x i16>* %A)  {
    ret void
 } 
 
-;CHECK: load_8_i8
+;CHECK-LABEL: load_8_i8:
 ;CHECK: pmovzxbw
 ;CHECK: paddw
 ;CHECK: pshufb

diff --git a/test/CodeGen/X86/v8i1-masks.ll b/test/CodeGen/X86/v8i1-masks.ll
index 8cbfb5d7243af16063fb3ee76676c4182b28bd2a..5da6e9636ebef00376b33e524bc46b2c463d182b 100644 (file)
--- a/test/CodeGen/X86/v8i1-masks.ll
+++ b/test/CodeGen/X86/v8i1-masks.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
 
-;CHECK: and_masks
+;CHECK-LABEL: and_masks:
 ;CHECK: vmovaps
 ;CHECK: vcmpltp
 ;CHECK: vcmpltp

diff --git a/test/CodeGen/X86/vec_cast2.ll b/test/CodeGen/X86/vec_cast2.ll
index 08eb16f6313ba14d90e1dee81bc89853b66ae491..5f6e7a853a332e7f7fcd297d9f92ae73b24695d9 100644 (file)
--- a/test/CodeGen/X86/vec_cast2.ll
+++ b/test/CodeGen/X86/vec_cast2.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 
-;CHECK: foo1_8
+;CHECK-LABEL: foo1_8:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <8 x float> @foo1_8(<8 x i8> %src) {
@@ -8,7 +8,7 @@ define <8 x float> @foo1_8(<8 x i8> %src) {
   ret <8 x float> %res
 }
 
-;CHECK: foo1_4
+;CHECK-LABEL: foo1_4:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <4 x float> @foo1_4(<4 x i8> %src) {
@@ -16,7 +16,7 @@ define <4 x float> @foo1_4(<4 x i8> %src) {
   ret <4 x float> %res
 }
 
-;CHECK: foo2_8
+;CHECK-LABEL: foo2_8:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <8 x float> @foo2_8(<8 x i8> %src) {
@@ -24,7 +24,7 @@ define <8 x float> @foo2_8(<8 x i8> %src) {
   ret <8 x float> %res
 }
 
-;CHECK: foo2_4
+;CHECK-LABEL: foo2_4:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <4 x float> @foo2_4(<4 x i8> %src) {
@@ -32,14 +32,14 @@ define <4 x float> @foo2_4(<4 x i8> %src) {
   ret <4 x float> %res
 }
 
-;CHECK: foo3_8
+;CHECK-LABEL: foo3_8:
 ;CHECK: vcvttps2dq
 ;CHECK: ret
 define <8 x i8> @foo3_8(<8 x float> %src) {
   %res = fptosi <8 x float> %src to <8 x i8>
   ret <8 x i8> %res
 }
-;CHECK: foo3_4
+;CHECK-LABEL: foo3_4:
 ;CHECK: vcvttps2dq
 ;CHECK: ret
 define <4 x i8> @foo3_4(<4 x float> %src) {