CLK: SPEAr: Add missing clocks
authorVipul Kumar Samar <vipulkumar.samar@st.com>
Sat, 10 Nov 2012 06:43:44 +0000 (12:13 +0530)
committerMike Turquette <mturquette@linaro.org>
Wed, 21 Nov 2012 19:45:52 +0000 (11:45 -0800)
This patch adds missing clocks: twd and macb.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/spear/spear1310_clock.c
drivers/clk/spear/spear1340_clock.c
drivers/clk/spear/spear3xx_clock.c

index 2809b670e22cf6a356372bd431505cedb1e30712..b64d51153a7862b6d9fb67696367c433e36222dc 100644 (file)
@@ -491,6 +491,10 @@ void __init spear1310_clk_init(void)
                        2);
        clk_register_clkdev(clk, NULL, "ec800620.wdt");
 
+       clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
+                       2);
+       clk_register_clkdev(clk, NULL, "smp_twd");
+
        clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
                        6);
        clk_register_clkdev(clk, "ahb_clk", NULL);
index aa5ed435fbad91c022fe1ca998f6551970088a96..8f00533959a50c20076b5d0c0310748180a23945 100644 (file)
@@ -535,6 +535,10 @@ void __init spear1340_clk_init(void)
                        2);
        clk_register_clkdev(clk, NULL, "ec800620.wdt");
 
+       clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
+                       2);
+       clk_register_clkdev(clk, NULL, "smp_twd");
+
        clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
                        ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
                        SPEAR1340_HCLK_SRC_SEL_SHIFT,
index 4c89b143e246bb596b9c46b4d959fc45ab1b3202..ff35ebca1d8d648219e2b1fd8a119f4f226fbfb6 100644 (file)
@@ -288,6 +288,14 @@ static void __init spear320_clk_init(void)
                        4);
        clk_register_clkdev(clk, "i2s_sclk", NULL);
 
+       clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, "hclk", "aa000000.eth");
+
+       clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, "hclk", "ab000000.eth");
+
        clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
                        ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
                        SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,