remove MachineOpCode typedef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index d47ee740b6381ac80bdd5af5239b5dac947b3086..d8aff40fa1c35e9c8ca95aef9fce917b8d54ed51 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -32,12 +32,6 @@ class SelectionDAG;
 
 template<class T> class SmallVectorImpl;
 
-//===----------------------------------------------------------------------===//
-// Data types used to define information about a single machine instruction
-//===----------------------------------------------------------------------===//
-
-typedef short MachineOpCode;
-
 //===----------------------------------------------------------------------===//
 // struct TargetInstrDescriptor:
 //  Predefined information about each machine instruction.

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 35226379e1cee8ea3bb73c1cecbda13f4aa1ba8b..b291d19d86531f168f0ba06ca1ffa735b923f904 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -52,7 +52,7 @@ const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
 ///
 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
                                unsigned &SrcReg, unsigned &DstReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   switch (oc) {
   default:
     return false;

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index abd7e33a6948efd5e86f671f7ea764296df8d514..53d710487039dc7c831e0f78cf6b078356670ab1 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,7 @@ AlphaInstrInfo::AlphaInstrInfo()
 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
                                  unsigned& sourceReg,
                                  unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == Alpha::BISr   || 
       oc == Alpha::CPYSS  || 
       oc == Alpha::CPYST  ||

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index e9b263f0c9dcfd6a58535a50445b2dc698e34662..e72cd1243c52220b25ac0c189c58eea75c36b867 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -225,7 +225,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                      unsigned SrcReg, bool isKill, int FrameIdx,
                                      const TargetRegisterClass *RC) const
 {
-  MachineOpCode opc;
+  unsigned opc;
   if (RC == SPU::GPRCRegisterClass) {
     opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
       ? SPU::STQDr128
@@ -308,7 +308,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         unsigned DestReg, int FrameIdx,
                                         const TargetRegisterClass *RC) const
 {
-  MachineOpCode opc;
+  unsigned opc;
   if (RC == SPU::GPRCRegisterClass) {
     opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
       ? SPU::LQDr128

diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index f33b5da9ed79ecae279e010f52611cdc45c08b70..2ba2c8fe1d6c6c5b6f2c4a516f668db72c777527 100644 (file)
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -27,7 +27,7 @@ IA64InstrInfo::IA64InstrInfo()
 bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == IA64::MOV || oc == IA64::FMOV) {
   // TODO: this doesn't detect predicate moves
      assert(MI.getNumOperands() >= 2 &&

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 4d404a547ff2bf70568d0f4ce13300532f30224a..47e28710176f2fc579fc4b74d27ff6f9afe8f96a 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -37,7 +37,7 @@ const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
     assert(MI.getNumOperands() >= 3 &&

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index d79c1edf9f48e48cdffe0084bdc9f741391c881a..eb455ca8da6c3655b7c198baf5a223b5e997ff46 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -636,7 +636,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
       oc == X86::MOV32rr || oc == X86::MOV64rr ||
       oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||

diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index ccee43d6bba915c7fb09b46f1ca8234445089e99..c0aefb41477c92cfc21d37265cfaaf8b8a5d2cd2 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -367,7 +367,7 @@ public:
   unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
     return TID->TSFlags >> X86II::OpcodeShift;
   }
-  unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const {
+  unsigned char getBaseOpcodeFor(unsigned Opcode) const {
     return getBaseOpcodeFor(&get(Opcode));
   }