VINTRPe_vi <op>,
SIMCInstr<opName, SISubtarget.VI>;
-multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
+multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
list<dag> pattern = [],
string disableEncoding = "", string constraints = ""> {
let DisableEncoding = disableEncoding,
Constraints = constraints in {
- def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
+ def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
- def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
+ def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
- def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
+ def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
}
}
// FIXME: Specify SchedRW for VINTRP insturctions.
defm V_INTERP_P1_F32 : VINTRP_m <
- 0x00000000, "v_interp_p1_f32",
+ 0x00000000,
(outs VGPR_32:$dst),
(ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
"v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
(i32 imm:$attr)))]>;
defm V_INTERP_P2_F32 : VINTRP_m <
- 0x00000001, "v_interp_p2_f32",
+ 0x00000001,
(outs VGPR_32:$dst),
(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
"$src0 = $dst">;
defm V_INTERP_MOV_F32 : VINTRP_m <
- 0x00000002, "v_interp_mov_f32",
+ 0x00000002,
(outs VGPR_32:$dst),
(ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
"v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",