#include <linux/mtd/partitions.h>\r
\r
#include "devices.h"\r
+#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"\r
+\r
\r
+ /* Set memory size of pmem */\r
+ #define SDRAM_SIZE SZ_128M\r
+ #define PMEM_GPU_SIZE (12 * SZ_1M)\r
+ #define PMEM_UI_SIZE SZ_16M\r
+ #define PMEM_VPU_SIZE SZ_32M\r
+ \r
+ #define PMEM_GPU_BASE (RK29_SDRAM_PHYS + SDRAM_SIZE - PMEM_GPU_SIZE)\r
+ #define PMEM_UI_BASE (PMEM_GPU_BASE - PMEM_UI_SIZE)\r
+ #define PMEM_VPU_BASE (PMEM_UI_BASE - PMEM_VPU_SIZE)\r
+ #define LINUX_SIZE (PMEM_VPU_BASE - RK29_SDRAM_PHYS)\r
+ \r
extern struct sys_timer rk29_timer;\r
\r
+ int rk29_nand_io_init(void)\r
+ {\r
+ return 0;\r
+ }\r
+ \r
+ struct rk29_nand_platform_data rk29_nand_data = {\r
+ .width = 1, /* data bus width in bytes */\r
+ .hw_ecc = 1, /* hw ecc 0: soft ecc */\r
+ .num_flash = 1,\r
+ .io_init = rk29_nand_io_init,\r
+ };\r
\r
static struct rk29_gpio_bank rk29_gpiobankinit[] = {\r
{\r
}, \r
};\r
\r
-#ifdef CONFIG_VIVANTE
-static struct resource resources_gpu[] = {
- [0] = {
- .name = "gpu_irq",
- .start = IRQ_GPU,
- .end = IRQ_GPU,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .name = "gpu_base",
- .start = RK29_GPU_PHYS,
- .end = RK29_GPU_PHYS + (256 << 10),
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .name = "gpu_mem",
+ /*****************************************************************************************\r
+ * lcd devices\r
+ * author: zyw@rock-chips.com\r
+ *****************************************************************************************/\r
+ //#ifdef CONFIG_LCD_TD043MGEA1\r
+ #define LCD_TXD_PIN RK29_PIN0_PA6 // ÂÒÌî,µÃÐÞ¸Ä\r
+ #define LCD_CLK_PIN RK29_PIN0_PA7 // ÂÒÌî,µÃÐÞ¸Ä\r
+ #define LCD_CS_PIN RK29_PIN0_PB6 // ÂÒÌî,µÃÐÞ¸Ä\r
+ #define LCD_TXD_MUX_NAME GPIOE_U1IR_I2C1_NAME\r
+ #define LCD_CLK_MUX_NAME NULL\r
+ #define LCD_CS_MUX_NAME GPIOH6_IQ_SEL_NAME\r
+ #define LCD_TXD_MUX_MODE 0\r
+ #define LCD_CLK_MUX_MODE 0\r
+ #define LCD_CS_MUX_MODE 0\r
+ //#endif\r
+ static int rk29_lcd_io_init(void)\r
+ {\r
+ int ret = 0;\r
+ \r
+ #if 0\r
+ rk29_mux_api_set(LCD_CS_MUX_NAME, LCD_CS_MUX_MODE);\r
+ if (LCD_CS_PIN != INVALID_GPIO) {\r
+ ret = gpio_request(LCD_CS_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ goto err1;\r
+ printk(">>>>>> lcd cs gpio_request err \n ");\r
+ }\r
+ }\r
+ \r
+ rk29_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE);\r
+ if (LCD_CLK_PIN != INVALID_GPIO) {\r
+ ret = gpio_request(LCD_CLK_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ goto err2;\r
+ printk(">>>>>> lcd clk gpio_request err \n ");\r
+ }\r
+ }\r
+ \r
+ rk29_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE);\r
+ if (LCD_TXD_PIN != INVALID_GPIO) {\r
+ ret = gpio_request(LCD_TXD_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ goto err3;\r
+ printk(">>>>>> lcd txd gpio_request err \n ");\r
+ }\r
+ }\r
+ \r
+ return 0;\r
+ \r
+ err3:\r
+ if (LCD_CLK_PIN != INVALID_GPIO) {\r
+ gpio_free(LCD_CLK_PIN);\r
+ }\r
+ err2:\r
+ if (LCD_CS_PIN != INVALID_GPIO) {\r
+ gpio_free(LCD_CS_PIN);\r
+ }\r
+ err1:\r
+ #endif\r
+ return ret;\r
+ }\r
+ \r
+ static int rk29_lcd_io_deinit(void)\r
+ {\r
+ int ret = 0;\r
+ #if 0\r
+ gpio_direction_output(LCD_CLK_PIN, 0);\r
+ gpio_set_value(LCD_CLK_PIN, GPIO_HIGH);\r
+ gpio_direction_output(LCD_TXD_PIN, 0);\r
+ gpio_set_value(LCD_TXD_PIN, GPIO_HIGH);\r
+ \r
+ gpio_free(LCD_CS_PIN);\r
+ rk29_mux_api_mode_resume(LCD_CS_MUX_NAME);\r
+ gpio_free(LCD_CLK_PIN);\r
+ gpio_free(LCD_TXD_PIN);\r
+ rk29_mux_api_mode_resume(LCD_TXD_MUX_NAME);\r
+ rk29_mux_api_mode_resume(LCD_CLK_MUX_NAME);\r
+ #endif\r
+ return ret;\r
+ }\r
+ \r
+ struct rk29lcd_info rk29_lcd_info = {\r
+ //.txd_pin = LCD_TXD_PIN,\r
+ //.clk_pin = LCD_CLK_PIN,\r
+ //.cs_pin = LCD_CS_PIN,\r
+ .io_init = rk29_lcd_io_init,\r
+ .io_deinit = rk29_lcd_io_deinit,\r
+ };\r
+ \r
+ \r
+ /*****************************************************************************************\r
+ * frame buffe devices\r
+ * author: zyw@rock-chips.com\r
+ *****************************************************************************************/\r
+ \r
+ #define FB_ID 0\r
+ #define FB_DISPLAY_ON_PIN RK29_PIN0_PB1 // ÂÒÌî,µÃÐÞ¸Ä\r
+ #define FB_LCD_STANDBY_PIN INVALID_GPIO\r
+ #define FB_MCU_FMK_PIN INVALID_GPIO\r
+ \r
+ #if 0\r
+ #define FB_DISPLAY_ON_VALUE GPIO_LOW\r
+ #define FB_LCD_STANDBY_VALUE 0\r
+ \r
+ #define FB_DISPLAY_ON_MUX_NAME GPIOB1_SMCS1_MMC0PCA_NAME\r
+ #define FB_DISPLAY_ON_MUX_MODE IOMUXA_GPIO0_B1\r
+ \r
+ #define FB_LCD_STANDBY_MUX_NAME NULL\r
+ #define FB_LCD_STANDBY_MUX_MODE 1\r
+ \r
+ #define FB_MCU_FMK_PIN_MUX_NAME NULL\r
+ #define FB_MCU_FMK_MUX_MODE 0\r
+ \r
+ #define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME\r
+ #define FB_DATA0_16_MUX_MODE 1\r
+ \r
+ #define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME\r
+ #define FB_DATA17_18_MUX_MODE 1\r
+ \r
+ #define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME\r
+ #define FB_DATA19_24_MUX_MODE 1\r
+ \r
+ #define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME\r
+ #define FB_DEN_MUX_MODE 1\r
+ \r
+ #define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME\r
+ #define FB_VSYNC_MUX_MODE 1\r
+ \r
+ #define FB_MCU_FMK_MUX_NAME NULL\r
+ #define FB_MCU_FMK_MUX_MODE 0\r
+ #endif\r
+ static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)\r
+ {\r
+ int ret = 0;\r
+ #if 0\r
+ if(fb_setting->data_num <=16)\r
+ rk29_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE);\r
+ if(fb_setting->data_num >16 && fb_setting->data_num<=18)\r
+ rk29_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE);\r
+ if(fb_setting->data_num >18)\r
+ rk29_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE);\r
+ \r
+ if(fb_setting->vsync_en)\r
+ rk29_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE);\r
+ \r
+ if(fb_setting->den_en)\r
+ rk29_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE);\r
+ \r
+ if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO))\r
+ {\r
+ rk29_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE);\r
+ ret = gpio_request(FB_MCU_FMK_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(FB_MCU_FMK_PIN);\r
+ printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");\r
+ }\r
+ gpio_direction_input(FB_MCU_FMK_PIN);\r
+ }\r
+ \r
+ if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO))\r
+ {\r
+ rk29_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE);\r
+ ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(FB_DISPLAY_ON_PIN);\r
+ printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");\r
+ }\r
+ }\r
+ \r
+ if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO))\r
+ {\r
+ rk29_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE);\r
+ ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);\r
+ if(ret != 0)\r
+ {\r
+ gpio_free(FB_LCD_STANDBY_PIN);\r
+ printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");\r
+ }\r
+ }\r
+ #endif\r
+ return ret;\r
+ }\r
+ \r
+ struct rk29fb_info rk29_fb_info = {\r
+ .fb_id = FB_ID,\r
+ //.disp_on_pin = FB_DISPLAY_ON_PIN,\r
+ //.disp_on_value = FB_DISPLAY_ON_VALUE,\r
+ //.standby_pin = FB_LCD_STANDBY_PIN,\r
+ //.standby_value = FB_LCD_STANDBY_VALUE,\r
+ //.mcu_fmk_pin = FB_MCU_FMK_PIN,\r
+ .lcd_info = &rk29_lcd_info,\r
+ .io_init = rk29_fb_io_init,\r
+ };\r
+ \r
+ static struct android_pmem_platform_data android_pmem_pdata = {\r
+ .name = "pmem",\r
+ .start = PMEM_UI_BASE,\r
+ .size = PMEM_UI_SIZE,\r
+ .no_allocator = 0,\r
+ .cached = 1,\r
+ };\r
+ \r
+ static struct platform_device android_pmem_device = {\r
+ .name = "android_pmem",\r
+ .id = 0,\r
+ .dev = {\r
+ .platform_data = &android_pmem_pdata,\r
+ },\r
+ };\r
+ \r
+ \r
+ static struct android_pmem_platform_data android_pmem_vpu_pdata = {\r
+ .name = "pmem_vpu",\r
+ .start = PMEM_VPU_BASE,\r
+ .size = PMEM_VPU_SIZE,\r
+ .no_allocator = 0,\r
+ .cached = 1,\r
+ };\r
+ \r
+ static struct platform_device android_pmem_vpu_device = {\r
+ .name = "android_pmem",\r
+ .id = 2,\r
+ .dev = {\r
+ .platform_data = &android_pmem_vpu_pdata,\r
+ },\r
+ };\r
+ \r
+ /*****************************************************************************************\r
+ * SDMMC devices\r
+ *****************************************************************************************/\r
+ #ifdef CONFIG_SDMMC0_RK29\r
+ void rk29_sdmmc0_cfg_gpio(struct platform_device *dev)\r
+ {\r
+ rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);\r
+ rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);\r
+ rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);\r
+ rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);\r
+ rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);\r
+ rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);\r
+ rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);\r
+ }\r
+ \r
+ #define CONFIG_SDMMC0_USE_DMA\r
+ struct rk29_sdmmc_platform_data default_sdmmc0_data = {\r
+ .num_slots = 1,\r
+ .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|\r
+ MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33| \r
+ MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),\r
+ .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),\r
+ .io_init = rk29_sdmmc0_cfg_gpio,\r
+ .dma_name = "sd_mmc",\r
+ #ifdef CONFIG_SDMMC0_USE_DMA\r
+ .use_dma = 1,\r
+ #else\r
+ .use_dma = 0,\r
+ #endif\r
+ };\r
+ #endif\r
+ #ifdef CONFIG_SDMMC1_RK29\r
+ #define CONFIG_SDMMC1_USE_DMA\r
+ void rk29_sdmmc1_cfg_gpio(struct platform_device *dev)\r
+ {\r
+ rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);\r
+ rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);\r
+ rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);\r
+ rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);\r
+ rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);\r
+ rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);\r
+ }\r
+ \r
+ struct rk29_sdmmc_platform_data default_sdmmc1_data = {\r
+ .num_slots = 1,\r
+ .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|\r
+ MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|\r
+ MMC_VDD_32_33|MMC_VDD_33_34),\r
+ .host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|\r
+ MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),\r
+ .io_init = rk29_sdmmc1_cfg_gpio,\r
+ .dma_name = "sdio",\r
+ #ifdef CONFIG_SDMMC1_USE_DMA\r
+ .use_dma = 1,\r
+ #else\r
+ .use_dma = 0,\r
+ #endif\r
+ };\r
+ #endif\r
+ \r
- .flags = IORESOURCE_MEM,
- },
-};
-struct platform_device rk29_device_gpu = {
- .name = "galcore",
- .id = 0,
- .num_resources = ARRAY_SIZE(resources_gpu),
- .resource = resources_gpu,
-};
++#ifdef CONFIG_VIVANTE\r
++static struct resource resources_gpu[] = {\r
++ [0] = {\r
++ .name = "gpu_irq",\r
++ .start = IRQ_GPU,\r
++ .end = IRQ_GPU,\r
++ .flags = IORESOURCE_IRQ,\r
++ },\r
++ [1] = {\r
++ .name = "gpu_base",\r
++ .start = RK29_GPU_PHYS,\r
++ .end = RK29_GPU_PHYS + (256 << 10),\r
++ .flags = IORESOURCE_MEM,\r
++ },\r
++ [2] = {\r
++ .name = "gpu_mem",\r
+ .start = PMEM_GPU_BASE,\r
+ .end = PMEM_GPU_BASE + PMEM_GPU_SIZE,\r
++ .flags = IORESOURCE_MEM,\r
++ },\r
++};\r
++struct platform_device rk29_device_gpu = {\r
++ .name = "galcore",\r
++ .id = 0,\r
++ .num_resources = ARRAY_SIZE(resources_gpu),\r
++ .resource = resources_gpu,\r
++};\r
+ #endif\r
+ \r
+ static void __init rk29_board_iomux_init(void)\r
+ {\r
+ #ifdef CONFIG_UART0_RK29 \r
+ rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT);\r
+ rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN);\r
+ #ifdef CONFIG_UART0_CTS_RTS_RK29\r
+ rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N);\r
+ rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N);\r
+ #endif\r
+ #endif\r
+ #ifdef CONFIG_UART1_RK29 \r
+ rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);\r
+ rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);\r
+ #endif\r
+ #ifdef CONFIG_UART2_RK29 \r
+ rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT);\r
+ rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN);\r
+ #ifdef CONFIG_UART2_CTS_RTS_RK29\r
+ rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);\r
+ rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N);\r
+ #endif\r
+ #endif\r
+ #ifdef CONFIG_UART3_RK29 \r
+ rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT);\r
+ rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN);\r
+ #ifdef CONFIG_UART3_CTS_RTS_RK29\r
+ rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N);\r
+ rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);\r
+ #endif\r
+ #endif\r
+ }\r
+ \r
static struct platform_device *devices[] __initdata = {\r
- #ifdef CONFIG_UART1_RK29 \r
+ #ifdef CONFIG_UART1_RK29\r
&rk29_device_uart1,\r
#endif \r
+#ifdef CONFIG_SPIM_RK29XX\r
+ &rk29xx_device_spi0m,\r
+ &rk29xx_device_spi1m,\r
+#endif\r
+ #ifdef CONFIG_SDMMC0_RK29 \r
+ &rk29_device_sdmmc0,\r
+ #endif\r
+ #ifdef CONFIG_SDMMC1_RK29\r
+ &rk29_device_sdmmc1,\r
+ #endif\r
+ #ifdef CONFIG_MTD_NAND_RK29\r
+ &rk29_device_nand,\r
+ #endif\r
+ \r
+ #ifdef CONFIG_FB_RK29\r
+ &rk29_device_fb,\r
+ #endif\r
+ #ifdef CONFIG_VIVANTE\r
+ &rk29_device_gpu,\r
+ #endif\r
+ &android_pmem_device,\r
+ &android_pmem_vpu_device,\r
};\r
\r
+/*****************************************************************************************\r
+ * spi devices\r
+ * author: cmc@rock-chips.com\r
+ *****************************************************************************************/\r
+#define SPI_CHIPSELECT_NUM 2\r
+struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {\r
+ {\r
+ .name = "spi0 cs0",\r
+ .cs_gpio = RK29_PIN2_PC1,\r
+ .cs_iomux_name = NULL,\r
+ },\r
+ {\r
+ .name = "spi0 cs1",\r
+ .cs_gpio = RK29_PIN1_PA4,\r
+ .cs_iomux_name = GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,//if no iomux,set it NULL\r
+ .cs_iomux_mode = GPIO1L_SPI0_CSN1,\r
+ }\r
+};\r
+\r
+struct spi_cs_gpio rk29xx_spi1_cs_gpios[SPI_CHIPSELECT_NUM] = {\r
+ {\r
+ .name = "spi1 cs0",\r
+ .cs_gpio = RK29_PIN2_PC5,\r
+ .cs_iomux_name = NULL,\r
+ },\r
+ {\r
+ .name = "spi1 cs1",\r
+ .cs_gpio = RK29_PIN1_PA3,\r
+ .cs_iomux_name = GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,//if no iomux,set it NULL\r
+ .cs_iomux_mode = GPIO1L_SPI0_CSN1,\r
+ }\r
+};\r
+\r
+static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)\r
+{ \r
+ int i,j,ret;\r
+ \r
+ //cs\r
+ if (cs_gpios) {\r
+ for (i=0; i<cs_num; i++) {\r
+ rk29_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);\r
+ ret = gpio_request(cs_gpios[i].cs_gpio, cs_gpios[i].name);\r
+ if (ret) {\r
+ for (j=0;j<i;j++) {\r
+ gpio_free(cs_gpios[j].cs_gpio);\r
+ //rk29_mux_api_mode_resume(cs_gpios[j].cs_iomux_name);\r
+ }\r
+ printk("[fun:%s, line:%d], gpio request err\n", __func__, __LINE__);\r
+ return -1;\r
+ } \r
+ gpio_direction_output(cs_gpios[i].cs_gpio, GPIO_HIGH);\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)\r
+{\r
+ int i;\r
+ \r
+ if (cs_gpios) {\r
+ for (i=0; i<cs_num; i++) {\r
+ gpio_free(cs_gpios[i].cs_gpio);\r
+ //rk29_mux_api_mode_resume(cs_gpios[i].cs_iomux_name);\r
+ }\r
+ }\r
+ \r
+ return 0;\r
+}\r
+\r
+static int spi_io_fix_leakage_bug(void)\r
+{\r
+ gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW); \r
+ return 0;\r
+}\r
+\r
+static int spi_io_resume_leakage_bug(void)\r
+{\r
+ gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);\r
+ return 0;\r
+}\r
+\r
+struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {\r
+ .num_chipselect = SPI_CHIPSELECT_NUM,\r
+ .chipselect_gpios = rk29xx_spi0_cs_gpios,\r
+ .io_init = spi_io_init,\r
+ .io_deinit = spi_io_deinit,\r
+ .io_fix_leakage_bug = spi_io_fix_leakage_bug,\r
+ .io_resume_leakage_bug = spi_io_resume_leakage_bug,\r
+};\r
+\r
+struct rk29xx_spi_platform_data rk29xx_spi1_platdata = {\r
+ .num_chipselect = SPI_CHIPSELECT_NUM,\r
+ .chipselect_gpios = rk29xx_spi1_cs_gpios,\r
+ .io_init = spi_io_init,\r
+ .io_deinit = spi_io_deinit,\r
+ .io_fix_leakage_bug = spi_io_fix_leakage_bug,\r
+ .io_resume_leakage_bug = spi_io_resume_leakage_bug,\r
+};\r
+\r
+/*****************************************************************************************\r
+ * xpt2046 touch panel\r
+ * author: cmc@rock-chips.com\r
+ *****************************************************************************************/\r
+#define XPT2046_GPIO_INT RK29_PIN0_PA3\r
+#define DEBOUNCE_REPTIME 3\r
+\r
+#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) \r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 0,\r
+ .x_min = 0,\r
+ .x_max = 320,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 0,\r
+ .x_min = 0,\r
+ .x_max = 320,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) \r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 1,\r
+ .x_min = 0,\r
+ .x_max = 800,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+ \r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)\r
+static struct xpt2046_platform_data xpt2046_info = {\r
+ .model = 2046,\r
+ .keep_vref_on = 1,\r
+ .swap_xy = 1,\r
+ .x_min = 0,\r
+ .x_max = 800,\r
+ .y_min = 0,\r
+ .y_max = 480,\r
+ .debounce_max = 7,\r
+ .debounce_rep = DEBOUNCE_REPTIME,\r
+ .debounce_tol = 20,\r
+ .gpio_pendown = XPT2046_GPIO_INT,\r
+ \r
+ .penirq_recheck_delay_usecs = 1,\r
+};\r
+#endif\r
+\r
+static struct spi_board_info board_spi_devices[] = {\r
+#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_CBN_SPI)\\r
+ ||defined(CONFIG_TOUCHSCREEN_XPT2046_SPI) || defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)\r
+ {\r
+ .modalias = "xpt2046_ts",\r
+ .chip_select = 0,\r
+ .max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */\r
+ .bus_num = 0,\r
+ .irq = XPT2046_GPIO_INT,\r
+ .platform_data = &xpt2046_info,\r
+ },\r
+#endif\r
+}; \r
+\r
+\r
static void __init rk29_gic_init_irq(void)\r
{\r
gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);\r
rk29_gpio_init(rk29_gpiobankinit, MAX_BANK);\r
rk29_gpio_irq_setup();\r
}\r
+ \r
static void __init machine_rk29_board_init(void)\r
{ \r
++ rk29_board_iomux_init();\r
platform_add_devices(devices, ARRAY_SIZE(devices)); \r
- rk29_board_iomux_init();\r
+ spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));\r
}\r
\r
+ static void __init machine_rk29_fixup(struct machine_desc *desc, struct tag *tags,\r
+ char **cmdline, struct meminfo *mi)\r
+ {\r
+ mi->nr_banks = 1;\r
+ mi->bank[0].start = RK29_SDRAM_PHYS;\r
+ mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS);\r
+ mi->bank[0].size = LINUX_SIZE;\r
+ }\r
+ \r
static void __init machine_rk29_mapio(void)\r
{\r
rk29_map_common_io();\r
#include <linux/delay.h>
#include <mach/irqs.h>
#include <mach/rk29_iomap.h>
+#include <mach/rk29-dma-pl330.h>
#include "devices.h"
-
+
++
+ #ifdef CONFIG_SDMMC0_RK29
+ static struct resource resources_sdmmc0[] = {
+ {
+ .start = IRQ_SDMMC,
+ .end = IRQ_SDMMC,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK29_SDMMC0_PHYS,
+ .end = RK29_SDMMC0_PHYS + RK29_SDMMC0_SIZE -1,
+ .flags = IORESOURCE_MEM,
+ }
+ };
+ #endif
+ #ifdef CONFIG_SDMMC1_RK29
+ static struct resource resources_sdmmc1[] = {
+ {
+ .start = IRQ_SDIO,
+ .end = IRQ_SDIO,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK29_SDMMC1_PHYS,
+ .end = RK29_SDMMC1_PHYS + RK29_SDMMC1_SIZE -1,
+ .flags = IORESOURCE_MEM,
+ }
+ };
+ #endif
+ /* sdmmc */
+ #ifdef CONFIG_SDMMC0_RK29
+ struct platform_device rk29_device_sdmmc0 = {
+ .name = "rk29_sdmmc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(resources_sdmmc0),
+ .resource = resources_sdmmc0,
+ .dev = {
+ .platform_data = &default_sdmmc0_data,
+ },
+ };
+ #endif
+ #ifdef CONFIG_SDMMC1_RK29
+ struct platform_device rk29_device_sdmmc1 = {
+ .name = "rk29_sdmmc",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(resources_sdmmc1),
+ .resource = resources_sdmmc1,
+ .dev = {
+ .platform_data = &default_sdmmc1_data,
+ },
+ };
+ #endif
/*
* rk29 4 uarts device
*/
};
#endif
+/*
+ * rk29xx spi master device
+ */
+static struct resource rk29_spi0_resources[] = {
+ {
+ .start = IRQ_SPI0,
+ .end = IRQ_SPI0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK29_SPI0_PHYS,
+ .end = RK29_SPI0_PHYS + RK29_SPI0_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DMACH_SPI0_TX,
+ .end = DMACH_SPI0_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ {
+ .start = DMACH_SPI0_RX,
+ .end = DMACH_SPI0_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device rk29xx_device_spi0m = {
+ .name = "rk29xx_spim",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(rk29_spi0_resources),
+ .resource = rk29_spi0_resources,
+ .dev = {
+ .platform_data = &rk29xx_spi0_platdata,
+ },
+};
+
+static struct resource rk29_spi1_resources[] = {
+ {
+ .start = IRQ_SPI1,
+ .end = IRQ_SPI1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK29_SPI1_PHYS,
+ .end = RK29_SPI1_PHYS + RK29_SPI1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DMACH_SPI1_TX,
+ .end = DMACH_SPI1_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ {
+ .start = DMACH_SPI1_RX,
+ .end = DMACH_SPI1_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device rk29xx_device_spi1m = {
+ .name = "rk29xx_spim",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(rk29_spi1_resources),
+ .resource = rk29_spi1_resources,
+ .dev = {
+ .platform_data = &rk29xx_spi1_platdata,
+ },
+};
+
+ #ifdef CONFIG_FB_RK29
+ /* rk29 fb resource */
+ static struct resource rk29_fb_resource[] = {
+ [0] = {
+ .start = RK29_LCDC_PHYS,
+ .end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_LCDC,
+ .end = IRQ_LCDC,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ /*platform_device*/
+ extern struct rk29fb_info rk29_fb_info;
+ struct platform_device rk29_device_fb = {
+ .name = "rk29-fb",
+ .id = 4,
+ .num_resources = ARRAY_SIZE(rk29_fb_resource),
+ .resource = rk29_fb_resource,
+ .dev = {
+ .platform_data = &rk29_fb_info,
+ }
+ };
+ #endif
+ #if defined(CONFIG_MTD_NAND_RK29)
+ static struct resource nand_resources[] = {
+ {
+ .start = RK29_NANDC_PHYS,
+ .end = RK29_NANDC_PHYS+RK29_NANDC_SIZE -1,
+ .flags = IORESOURCE_MEM,
+ }
+ };
+
+ struct platform_device rk29_device_nand = {
+ .name = "rk29-nand",
+ .id = -1,
+ .resource = nand_resources,
+ .num_resources= ARRAY_SIZE(nand_resources),
+ .dev = {
+ .platform_data= &rk29_nand_data,
+ },
+
+ };
+ #endif
projects / firefly-linux-kernel-4.4.55.git / commitdiff