Do not use register as base ptr of pre- and post- inc/dec load / store nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 1378f25387e32b10eb0deede475ce18914ab133d..10b7576a69c53aa67ce4d1c44abe8d2b1eac7a86 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4536,7 +4536,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
 
   // Check #1.  Preinc'ing a frame index would require copying the stack pointer
   // (plus the implicit offset) to a register to preinc anyway.
-  if (isa<FrameIndexSDNode>(BasePtr))
+  if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
     return false;
 
   // Check #2.
@@ -4663,6 +4663,9 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
       //    nor a successor of N. Otherwise, if Op is folded that would
       //    create a cycle.
 
+      if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
+        continue;
+
       // Check for #1.
       bool TryNext = false;
       for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),

diff --git a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
new file mode 100644 (file)
index 0000000..2bca6e6
--- /dev/null
+++ b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6
+; PR4166
+
+       %"byte[]" = type { i32, i8* }
+       %tango.time.Time.Time = type { i64 }
+
+define fastcc void @t() {
+entry:
+       %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null)            ; <i1> [#uses=0]
+       ret void
+}