// Set the "zero" bit in CPSR.
switch (MI->getOpcode()) {
default: break;
+ case ARM::RSBrr:
case ARM::RSBri:
+ case ARM::RSCrr:
case ARM::RSCri:
+ case ARM::ADDrr:
case ARM::ADDri:
+ case ARM::ADCrr:
case ARM::ADCri:
+ case ARM::SUBrr:
case ARM::SUBri:
+ case ARM::SBCrr:
case ARM::SBCri:
case ARM::t2RSBri:
+ case ARM::t2ADDrr:
case ARM::t2ADDri:
+ case ARM::t2ADCrr:
case ARM::t2ADCri:
+ case ARM::t2SUBrr:
case ARM::t2SUBri:
+ case ARM::t2SBCrr:
case ARM::t2SBCri: {
// Scan forward for the use of CPSR, if it's a conditional code requires
// checking of V bit, then this is not safe to do. If we can't find the
// fallthrough
}
+ case ARM::ANDrr:
case ARM::ANDri:
+ case ARM::t2ANDrr:
case ARM::t2ANDri:
// Toggle the optional operand to CPSR.
MI->getOperand(5).setReg(ARM::CPSR);
--- /dev/null
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
+
+; CHECK: _f
+; CHECK: adds
+; CHECK-NOT: cmp
+; CHECK: blxeq _g
+
+define i32 @f(i32 %a, i32 %b) nounwind ssp {
+entry:
+ %add = add nsw i32 %b, %a
+ %cmp = icmp eq i32 %add, 0
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void (...)* @g(i32 %a, i32 %b) nounwind
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret i32 %add
+}
+
+declare void @g(...)